Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter.

Abstract: A matte film for hot pressing and a manufacturing method thereof are provided. The manufacturing method includes steps of forming at least one polyester composition into an unstretched polyester thick film and stretching the unstretched polyester thick film in a machine direction (MD) and a transverse direction (TD). The polyester composition includes 81% to 97.9497% by weight of a polyester resin, 0.02% to 2% by weight of an antioxidative ingredient, 0.0003% to 1% by weight of a nucleating agent, 0.01% to 2% by weight of a flow aid, 0.01% to 2% by weight of a polyester modifier, 0.01% to 2% by weight of an inorganic filler, and 2% to 10% by weight of silica particles. The polyester resin has an intrinsic viscosity between 0.60 dl/g and 0.80 dl/g.

Abstract: The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.

Abstract: A raised floor and an assembling method thereof includes a plurality of raised floor boards, wherein a plurality of raised floor boards are assembled and connected to form an integrated floor, an edge of the integrated floor close to the wall is supported by a leveling beam, and leveling screws are arranged below connecting positions of two adjacent raised floor boards, a reserved expansion joint is arranged between the edge of the integrated floor and the wall, and a position above the integrated floor close to the wall is fixedly connected with frame beam by an expansion screw. An edge of the raised floor board body structure is processed, so that the raised floor boards can be assembled through lap joint and connection of structures, and supported through the leveling screws when they are in mutually lap joint for assembly.

Abstract: A method for forming a semiconductor structure includes: a base is provided, the base including a first area and a second area located outside the first area, the first area including stack structures and first isolation structures arranged alternately in a first direction, each stack structure including first semiconductor layers and second semiconductor layers stacked onto one another alternately in a third direction, the first direction being a direction in a plane where the base is located, the third direction intersecting with the plane where the base is located; the first semiconductor layers located in the first area, and the first isolation structures located in the first area and located in projection areas of the first semiconductor layers in the first direction are successively removed, to form active dummy connection layers extending in the first direction; and gate structures are formed on surfaces of the active dummy connection layers.

Abstract: A method for forming a semiconductor structure is provided. The method includes: providing a base, the base including a first area and second areas located outside the first area, the first area including stack structures and isolation trenches alternately arranged in a first direction, the first direction being any direction in a plane where the base is located; performing ion implantation on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches; and forming a gate structure on a surface of the active virtual connecting layer.

Abstract: A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.

Abstract: A device for reducing noise in a radio signal received in the FM band is proposed, including: a module for demodulating the radio signal, adapted to generate a demodulated radio signal on the basis of the received radio signal; a noise suppression module adapted to replace a temporal sequence of the demodulated radio signal with a denoised sequence; a module for controlling the noise suppression module, adapted to control the activation of the noise suppression module. The noise reduction device further including a module for analyzing the frequency spectrum of the received radio signal. The control module is configured to control the noise suppression module according to an activation strategy chosen from among several predetermined activation strategies depending on the spectral content of the received radio signal.

Abstract: This application provides an interface calling simulation method for developing an application program performed by an electronic device. The electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The electronic device identifies, within a simulated interface set for a simulation interface corresponding to the target interface. The simulated interface set includes simulated interfaces that simulate real interfaces in the application program. The electronic device compares the interface calling information of the target interface with interface configuration information of the simulated interface.

Abstract: Methods, systems, and apparatuses for erosion rate monitoring for wafer fabrication equipment are described to support determining a real-time edge ring erosion rate for an edge ring used in manufacturing memory devices or other semiconductor devices. A manufacturing system may support a real-time edge ring erosion rate determination using force sensors, which may measure the weight of the edge ring. The controller may correlate the measured weight to a height of the edge ring. The controller may use the height to adjust a vertical placement of the edge ring, or one or more other manufacturing variables, during manufacturing operations, which may compensate for edge ring erosion and reduce or eliminate yield loss when manufacturing a memory device or other semiconductor device.

Abstract: A three-dimensional semiconductor structure and a method for forming the same are provided. The method includes the following operations. A stack structure in a source region and a drain region is etched to form a plurality of parallel first trenches extending in the first direction in the stack structure in the source region and the drain region, in which a plurality of semiconductor layers retained in the channel region serve as a plurality of channel body layers. The channel body layers extend in a second direction, and each includes a plurality of channel areas arranged in the second direction. A through via is formed in an end of the channel body layers in the second direction and penetrates the end. A conductive material is filled in the through via to form a grounded conductive plug.

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.

Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.

Abstract: A memory device and a fabrication method thereof are provided. The memory device includes a substrate, a seed layer over the substrate, a superlattice structure in contact with the seed layer and a top electrode over the superlattice structure. The seed layer comprises carbon and silicon. The superlattice structure comprises first metal layers and second metal layers stacked alternately.

Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.

Abstract: The present disclosure relates to an antibody against Aquaporin-4 (AQP4). These peptide-specific AQP4 antibodies play a role to create a NMO model and contribute for investigating the NMO disease mechanisms and developing the strategy of the treatment.