Abstract: A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.

Abstract: A device for reducing noise in a radio signal received in the FM band is proposed, including: a module for demodulating the radio signal, adapted to generate a demodulated radio signal on the basis of the received radio signal; a noise suppression module adapted to replace a temporal sequence of the demodulated radio signal with a denoised sequence; a module for controlling the noise suppression module, adapted to control the activation of the noise suppression module. The noise reduction device further including a module for analyzing the frequency spectrum of the received radio signal. The control module is configured to control the noise suppression module according to an activation strategy chosen from among several predetermined activation strategies depending on the spectral content of the received radio signal.

Abstract: This application provides an interface calling simulation method for developing an application program performed by an electronic device. The electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The electronic device identifies, within a simulated interface set for a simulation interface corresponding to the target interface. The simulated interface set includes simulated interfaces that simulate real interfaces in the application program. The electronic device compares the interface calling information of the target interface with interface configuration information of the simulated interface.

Abstract: Methods, systems, and apparatuses for erosion rate monitoring for wafer fabrication equipment are described to support determining a real-time edge ring erosion rate for an edge ring used in manufacturing memory devices or other semiconductor devices. A manufacturing system may support a real-time edge ring erosion rate determination using force sensors, which may measure the weight of the edge ring. The controller may correlate the measured weight to a height of the edge ring. The controller may use the height to adjust a vertical placement of the edge ring, or one or more other manufacturing variables, during manufacturing operations, which may compensate for edge ring erosion and reduce or eliminate yield loss when manufacturing a memory device or other semiconductor device.

Abstract: A three-dimensional semiconductor structure and a method for forming the same are provided. The method includes the following operations. A stack structure in a source region and a drain region is etched to form a plurality of parallel first trenches extending in the first direction in the stack structure in the source region and the drain region, in which a plurality of semiconductor layers retained in the channel region serve as a plurality of channel body layers. The channel body layers extend in a second direction, and each includes a plurality of channel areas arranged in the second direction. A through via is formed in an end of the channel body layers in the second direction and penetrates the end. A conductive material is filled in the through via to form a grounded conductive plug.

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.

Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.

Abstract: A memory device and a fabrication method thereof are provided. The memory device includes a substrate, a seed layer over the substrate, a superlattice structure in contact with the seed layer and a top electrode over the superlattice structure. The seed layer comprises carbon and silicon. The superlattice structure comprises first metal layers and second metal layers stacked alternately.

Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.

Abstract: The present disclosure relates to an antibody against Aquaporin-4 (AQP4). These peptide-specific AQP4 antibodies play a role to create a NMO model and contribute for investigating the NMO disease mechanisms and developing the strategy of the treatment.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.

Abstract: A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.

Abstract: A fan-out package structure of an image sensing device includes an image sensing unit having an image sensor with opposite sensing surface and connecting surface, a spacer layer surrounding a central portion of the sensing surface, and a light-transmitting cover plate disposed on the spacer layer spaced apart from and covering the sensing surface. An image signal processor is disposed on the connecting surface. A redistribution layer covers the image signal processor and the connecting surface, and includes a fan-out area. An encapsulation layer is disposed on the fan-out area, surrounds and covers an outer periphery of the image sensing unit, and allows a top surface of the light-transmitting cover plate to be exposed. A method of manufacturing a fan-out package structure of an image sensing device is also disclosed.

Abstract: Water conservancy construction sewage treatment mechanism, including a support mounting cylinder, where a variable-diameter sedimentation cylinder is arranged at one end of the support mounting cylinder, one half of the cylinder wall of the support mounting cylinder is a thin wall and the other half is a thick wall, and the thin wall and the thick wall are disposed oppositely. The water conservancy construction sewage treatment mechanism also includes: a variable-diameter diversion cylinder, which is arranged on the thin wall at the other end of the support mounting cylinder; several displacement diversion modules, which are arranged on the thick wall of the support mounting cylinder and include guide displacement structures and combined diversion structures; and a magnetic attraction displacement adjusting structure, which is arranged on the outer side of the thick wall of the support mounting cylinder and is matched with the guide displacement structures and the combined diversion structures.

Abstract: Provided is a memory cell including a selector disposed over a substrate, a memory element and a connecting pad. The selector includes a bottom electrode, an ovonic threshold switch layer on the bottom electrode, an inter-electrode over the ovonic threshold switch layer, and an intermediate layer between the ovonic threshold switch layer and the inter-electrode. The memory element is disposed on the selector. The connecting pad is disposed on the memory element.

Abstract: A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.

Abstract: An ultrasonic device is provided and includes an action member, a driving member and a rotating shaft connected to the driving member. The action member provides ultrasonic vibration and vibrates the driving member, so that the driving member oscillates to make the rotating shaft and a cutter oscillate in the same direction together, so the cutter can remove scrap by oscillating during the cutting operation.

Abstract: The present disclosure relates to a heat radiator and a turbo fracturing unit comprising the same. The heat radiator includes: a cabin; a heat radiation core disposed at the inlet and configured to allow a gas/air to pass therethrough; a gas/air guide device disposed at the outlet and configured to suction the air within the cabin to the outlet; and noise reduction structure disposed within the cabin, which is of a structure progressively converging to the outlet. The heat radiator is configured to enable the gas/air to enter the cabin via the inlet, then sequentially pass through the heat radiation core, a surface of the noise reduction structure and the gas/air guide device, and finally be discharged out of the cabin. The heat radiator according to the present disclosure is a suction-type heat radiator which can regulate the speed of the gas/air guide device based on the temperature of the gas/air at the inlet, thereby avoiding energy waste and unnecessary noise.

Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.

Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. A top surface of the bottom electrode is located at a level height lower than that of a top surface of the first dielectric layer. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer contacts the top surface of the bottom electrode and the top surface of the first dielectric layer. The top electrode is disposed on the variable resistance layer.