Patents by Inventor Chen-An Cheng

Chen-An Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105654
    Abstract: A method of making a semiconductor device includes patterning a conductive layer over a substrate to define a conductive pad having a first width. The method includes depositing a passivation layer, wherein the passivation layer directly contacts the conductive pad. The method includes depositing a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The method includes depositing an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The method includes depositing a mask layer over the UBM layer; and forming an opening in the mask layer wherein the opening has the second width. The method includes forming a conductive pillar in the opening on the UBM layer; and etching the UBM layer using the conductive pillar as a mask, wherein the etched UBM layer has the second width.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Chita CHUANG, Yao-Chun CHUANG, Tsung-Shu LIN, Chen-Cheng KUO, Chen-Shien CHEN
  • Publication number: 20240106112
    Abstract: An antenna module is disposed to an electronic device includes a fixed member, a rotating component, a reflector, a director, and an antenna unit. The electronic device includes a first body and a second body. The first body has a first surface and a second surface. The fixed member is disposed to the first body fixedly. The rotating component is connected to the fixed member rotatably. The reflector and the director are disposed to the rotating component. The antenna unit is disposed to the first body and between the reflector and the director. When the first body and the second body rotate relative to each other, the reflector is located between the antenna unit and one of the first surface and the second surface, and the director is located between the antenna unit and another one of the first surface and the second surface.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 28, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Jo-Fan Chang, Yu Chen, Jhih-Ning Cheng, Yu-Hsun Huang
  • Publication number: 20240105632
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 11942699
    Abstract: An antenna device includes a first insulation layer, a defected metal layer, a second insulation layer, and a plurality of radiators. The defected metal layer is disposed on the first insulation layer, and the defected metal layer has a plurality of recess features which are arranged with uniform pitches. The second insulation layer is disposed on the first insulation layer and the defected metal layer. The radiators are disposed on the second insulation layer, and each radiator has a feeding portion and a grounding portion.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 26, 2024
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Hsin-Hung Lin, Wei Chen Cheng
  • Patent number: 11943785
    Abstract: A method for PDCCH monitoring performed by a UE is provided. The method includes performing the PDCCH monitoring in a first group associated with at least one first PDCCH monitoring configuration; receiving, from a base station, DCI comprising an indicator; performing the PDCCH monitoring in a second group associated with at least one second PDCCH monitoring configuration; and stopping the PDCCH monitoring in the first group after receiving the indicator.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 26, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Wan-Chen Lin, Chie-Ming Chou, Tsung-Hua Tsai, Yu-Hsin Cheng
  • Patent number: 11942652
    Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 26, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
  • Publication number: 20240096816
    Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20240097216
    Abstract: The present invention discloses a detection device and a probe module thereof, wherein an electrical connection path between a battery detection frame and a battery under test is provided via the probe module. The probe module includes a base, a first polarity plate, a second polarity plate, a first upper connection group, a second upper connection group, a first lower connection member and a second lower connection member. Via the first polarity plate, the first upper connection group is correspondingly coupled to the battery detection frame, and the first lower connection member is correspondingly coupled to the battery under test. Via the second polarity plate, the second upper connection group is correspondingly coupled to the battery detection frame, and the second lower connection member is correspondingly coupled to the battery under test. Thus, it is not necessary to process a cable having been fixed on the battery detection frame when the probe module is replaced.
    Type: Application
    Filed: June 8, 2023
    Publication date: March 21, 2024
    Inventors: CHUAN-TSE LIN, CHEN-CHOU WEN, SHIH-CHIN TAN, WEN-CHUAN CHANG, YING-CHENG CHEN
  • Publication number: 20240096834
    Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Inventors: Shih Hsuan HSU, Chan-Chung CHENG, Chun-Chen LIU, Cheng-Hung CHEN, Peng-Ren CHEN, Wen-Hao CHENG, Jong-l MOU
  • Publication number: 20240097351
    Abstract: The present disclosure provides an antenna system, which includes a defected ground structure board and an antenna structure board. The defected ground structure board includes a first insulating plate and a defected ground structure layer, and the defected ground structure layer is disposed on the first insulating plate. The antenna structure board is disposed on the defected ground structure board. The antenna structure board includes at least one antenna body and a second insulating plate, the at least one antenna body is disposed on the second insulating plate, and the second insulating plate is disposed on the defected ground structure layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: March 21, 2024
    Inventors: Hsin Hung LIN, Yu Shu TAI, Wei Chen CHENG
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240098791
    Abstract: Apparatus and methods are provided RLF detection for SL-U transceiving. In one novel aspect, HARQ-based RLF detection and/or LBT-based RLF detection is performed for SL-U RLF. HARQ based SL-U RLF procedure increases DTX for each PSSCH or PSCCH and disregards detected DTX on PSFCH or increases DTX for each PSFCH absence. In one embodiment, a DTX threshold value is modified. In one embodiment, the LBT based RLF procedure detects and reports an LBT failure for an RB set by the PHY layer; determines a consistent LBT (C-LBT) for the RB set based on a C-LBT threshold at the MAC layer and determines an RLF when all configured RB sets for the SL connection is determined to be C-LBT. In another novel aspect, multiple PSFCH occasions are configured for one PSSCH/PSCCH at a consecutive symbol level, a non-consecutive symbol level, a consecutive slot level or a non-consecutive slot level.
    Type: Application
    Filed: September 28, 2023
    Publication date: March 21, 2024
    Inventors: JUN-QIANG CHENG, Tao Chen, JING-WEI CHEN
  • Publication number: 20240096734
    Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tzu-Hsuan CHENG, Yong LIU, Liangbiao CHEN
  • Publication number: 20240091315
    Abstract: The present invention relates to extended recombinant polypeptide (XTEN) compositions, conjugate compositions comprising XTEN and XTEN linked to cross-linkers useful for conjugation to pharmacologically active payloads, methods of making highly purified XTEN, methods of making XTEN-linker and XTEN-payload conjugates, and methods of using the XTEN-cross-linker and XTEN-payload compositions.
    Type: Application
    Filed: March 13, 2023
    Publication date: March 21, 2024
    Inventors: Volker Schellenberger, Vladimir Podust, Chia-Wei Wang, Bryant McLaughlin, Bee-Cheng Sim, Sheng Ding, Chen Gu
  • Publication number: 20240096757
    Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Patent number: 11933945
    Abstract: An optical lens includes a first lens group and a second lens group. The first lens group has at least two lenses that include at least one aspheric lens, the second lens group has at least four lenses that includes at least one aspheric lens, and a total number of lenses with refractive powers in the optical lens is smaller than nine. The first and the second lens groups include a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens in order from the magnified side to the minified side. The first lens to the sixth lens have respective refractive powers of negative, negative, positive, positive, negative and positive.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 19, 2024
    Assignee: RAYS OPTICS INC.
    Inventors: Ching-Lung Lai, Ying-Hsiu Lin, Chen-Cheng Lee
  • Publication number: 20240089938
    Abstract: Apparatus and methods are provided for SL-U resource allocation and usage. In one novel aspect, one or two candidate starting symbols are configured. In one embodiment, the candidate starting symbols are preconfigured for AGC or a repetition of PSCCH/PSSCH data. In one embodiment, CAPC value is mapped from a PQI with a bitmap or a mapping table. The CAPC value is mapped from the PQI based on one or more elements comprising a resource type, a default priority level, a packet delay budget (PDB) requirement, and packet data error rate. In one novel aspect, multi-consecutive-slot (MCSt) resources are reserved for SL-U by applying one or more resource selection rules, comprising selecting, by a MAC layer, resources excluded by a PHY layer in an exclusion step, increasing one or more selection thresholds comprising a resource exclusion RSRP threshold, a remaining resource portion after resource exclusion threshold, and a RSRP threshold.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Inventors: JUN-QIANG CHENG, Tao Chen
  • Publication number: 20240087954
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Inventors: JING-CHENG LIN, YING-CHING SHIH, PU WANG, CHEN-HUA YU
  • Patent number: 11930663
    Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 12, 2024
    Assignee: Au Optronics Corporation
    Inventors: Bo-Chen Chen, Yun-Ru Cheng, Ya-Ling Hsu, Chia-Hsuan Pai, Cheng-Wei Huang, Wei-Shan Chao
  • Patent number: 11930543
    Abstract: A method of radio bearer transmission in dual connectivity for a network in a long term evolution (LTE) system comprises generating at least a packet data convergence protocol protocol data unit (PDCP PDU) by a PDCP entity of the network corresponding to a radio bearer (RB), and assigning each PDCP PDU with an identity, wherein the identity indicates which PDCP entity the PDCP PDU belongs to.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 12, 2024
    Assignee: ACER INCORPORATED
    Inventors: Hung-Chen Chen, Ching-Wen Cheng