Abstract: This document describes systems and techniques directed at an external wide-angle lens for imagers in electronic devices. An imager is disclosed that includes an image sensor and a lens stack, the lens stack including an external wide-angle lens, an internal lens, and four or more intermediate lenses. The imager has a first ratio of a projection at a vertex of the external wide-angle lens divided by a maximum focused dimension of the focal area being less than or equal to 0.15, a second ratio of a total length of the lens stack divided by the maximum focused dimension being less than or equal to 7.0, or a third ratio of a total transmission length of the imager divided by an entrance pupil diameter of the external wide-angle lens being between 1.2 and 2.6.

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes: providing a substrate comprising an array region and a peripheral region, wherein the array region and the peripheral region define a stepped structure, performing a deposition process to form a passivation layer over the array region and the peripheral region; performing an etching process to remove a portion of the passivation layer over the array region; and performing a chemical mechanical polishing process so that the passivation layer has a substantially continuous surface over the array region and the peripheral region.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes: providing a substrate comprising an array region and a peripheral region, wherein the array region and the peripheral region define a stepped structure, performing a deposition process to form a passivation layer over the array region and the peripheral region; performing an etching process to remove a portion of the passivation layer over the array region; and performing a chemical mechanical polishing process so that the passivation layer has a substantially continuous surface over the array region and the peripheral region.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.

Abstract: A system comprises a power source and two power rails coupled to the power source. A storage device, comprising a non-volatile memory, a cache coupled to the non-volatile memory, and a control pin, is coupled to the second power rail. A power management controller is coupled to the first power rail and to a control pin of the storage device. The power management controller stops the provision of power via the first power rail and provides a signal to the storage device via the control pin when the provision of power via the first power rail is stopped. The storage device continues to receive power from the second power rail when the provision of power via the first power rail is stopped. The storage device stores data from the cache to the non-volatile memory in response to the receipt of the signal via the control pin.

Abstract: A signal processing method and a signal processing apparatus are provided in the present application. A network device configures a paging early indication for a terminal device in an idle state, where the paging early indication is used for indicating monitoring of a physical downlink control channel (PDCCH) of at least one paging occasion, and/or monitoring of at least one PDCCH with different paging contents; after the network device sends the paging early indication to the terminal device, the terminal device can accurately indicate physical downlink control channel (PDCCH) monitoring at a paging occasion, which avoids unnecessary false wake-up or non-wake-up caused by a paging occasion conflict, thereby reducing power consumption of the terminal device.

Abstract: The present application provides a signal processing method and apparatus, where a network device configures a location of a paging indication signal for a terminal device in an idle state, after the network device transmits the paging indication signal to the terminal device according to the location of the paging indication signal, the terminal device may avoid consuming more energy caused by a relatively long distance between the location of the paging indication signal and a synchronization reference signal, and/or, the terminal device may avoid reducing the demodulation and decoding performance of the paging indication signal caused by a relatively long distance between the location of the paging indication signal and a channel time-frequency tracking reference signal.

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 ?m, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Abstract: An electronic device with an auxiliary illumination function and an operation method thereof are provided. The electronic device includes a first body, a display screen, a light-emitting module, and a processing module. The first body has a first surface. The first surface includes a screen area and a border area, and the border area surrounds the screen area. The display screen is disposed in the screen area of the first body. The light-emitting module is disposed in the border area of the first body. The processing module is disposed in the electronic device and is coupled to the display screen and the light-emitting module. The processing module activates the light-emitting module in the border area to emit an auxiliary illumination light according to a required condition.

Abstract: The present application discloses a detection model training method and apparatus. The method includes determining an initial training model; determining a training sample; determining whether a target object is present in a first image through the initial detection model according to a feature of a first image, to obtain a detection result; and determining a domain that an image in the training sample belongs to through the adaptive model according to a feature of an image, to obtain a domain classification result; calculating, a loss function value related to the initial training model according to the detection result, the domain classification result, a first identifier, a second identifier, and a third identifier; and adjusting a parameter value in the initial training model according to the loss function value, to obtain a final detection model.

Abstract: A multi-loop error amplifier circuit for generating an error amplification signal includes: a first operational transconductance amplifier (OTA) including a first current output stage which generates a first transconductance amplification current in a predetermined current direction according to a first voltage difference between a positive terminal and a negative input terminal of the first OTA; a second OTA including a second current output stage which generates a second transconductance amplification current in the predetermined current direction according to a second voltage difference between a positive terminal and a negative input terminal of the second OTA. The first and the second current output stages are coupled in series to generate a first error output current. The error amplification signal is generated according to the first error output current which is equal to the smaller one of the first and the second transconductance amplification currents.

Abstract: A touch display device includes a driving substrate, a display medium layer, a common electrode layer, a touch electrode layer, and a protective layer. The display medium layer is disposed on the driving substrate. The common electrode layer is in direct contact with and disposed on the display medium layer. The common electrode layer includes multiple common electrodes, and two adjacent of the common electrodes have a spacing between each other. The touch electrode layer is disposed on the display medium layer. The touch electrode layer and the common electrode layer define a touch structure layer. The protective layer is disposed on the touch electrode layer.

Abstract: Disclosed are a method and apparatus for determining an RA-RNTI. In the present application, a base station receives a random access preamble sent by a terminal; the base station determines an RA-RNTI according to a time-frequency resource occupied by the random access preamble, and the time-frequency resource is a time-frequency resource of an orthogonal frequency division multiplexing (OFDM) symbol level; and the base station sends a random access response message, and the random access response message includes downlink control information allocated, by the base station, for the terminal, and the downlink control information is scrambled using the RA-RNTI. By means of the present application, an RA-RNTI can be determined during a random access process of an NR system.

Abstract: A virtual reality providing device and an audio processing method are provided. The virtual reality providing device includes a casing, a first microphone, a controller, an audio controller, an image player, and an audio player. The first microphone is disposed at one side of the case to receive a first audio signal of a user. The audio controller is electrically connected to the first microphone and the controller. The controller obtains a first sound collection distance and a first sound collection angle based on a virtual sound collection position. The virtual sound collection position is different from a position of the first microphone. The controller adjusts the first audio signal based on the first sound collection distance and the first sound collection angle to generate an adjusted first audio signal, and the audio player plays the adjusted first audio signal.

Abstract: Disclosed are a method and device for transmitting a positioning reference signal. The method includes a base station determining a time-frequency resource for sending a PRS according to configuration information of the PRS, mapping a PRS sequence to the time-frequency resource for sending the PRS, and sending the mapped PRS on the time-frequency resource for sending the PRS, wherein the configuration information of the PRS comprises PRS frequency domain resource information; the PRS frequency domain resource information comprises PRS resource element (RE) frequency shift information, and the PRS RE frequency shift information is correlated with a PRS OFDM symbol index value calculated from a PRS occasion.