Abstract: A frequency detection apparatus and method are provided. The frequency detection apparatus includes a frequency conversion circuit and an analog conversion circuit. The frequency conversion circuit receives an input clock, and generates an analog signal corresponding to a frequency of the input clock based on the frequency of the input clock. The analog conversion circuit is coupled to the frequency conversion circuit, receives the analog signal, and generates a discriminating signal corresponding to the frequency of the input clock based on the analog signal, where the discriminating signal represents a frequency interval of the input clock.

Abstract: A transceiver in a full duplex communication system includes a hybrid circuit for transmitting a transmission signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmission signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC is directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Abstract: The present invention discloses a digital-to-analog converter (DAC), including a bias voltage generating unit, a digital-to-analog converting stage, and an operating amplifier. The bias voltage generating unit is utilized for generating a first bias voltage. The digital-to-analog converting stage is utilized for converting a digital signal into a voltage signal, the digital-to-analog converting stage includes a current source for providing a current, and a switching unit is coupled to the current source for controlling the current to pass the switching unit according to the digital signal, and a load. The current flows through the load to generate the voltage signal. The operating amplifier is coupled to the bias voltage generating unit and the digital-to-analog converting stage for controlling the current source according to the first bias voltage.

Abstract: A transmission line driver for generating an output signal to drive a transmission line is disclosed. The transmission line driver includes a voltage driver and a current driver. The voltage driver generates a voltage signal to drive the transmission line. The current driver generates a current signal to drive the transmission line. The amplitude of the output signal is determined according to the voltage signal and/or the current signal.

Abstract: This invention discloses a clock generator capable of automatically adjusting output clock when process, voltage, or temperature variation occurred. The clock generator comprises a current generator, for generating a first current and a second current according to a control voltage; a oscillator, coupled to the current generator, for generating a clock signal according to the first current; and a voltage adjuster, coupled to the current generator and the oscillator, for adjusting the control voltage according to the clock signal and the second current; wherein, when the signal frequency of the clock signal changed, the voltage adjuster correspondingly adjusts the control voltage so as to adjust the first current.

Abstract: An apparatus for echo cancellation in a transceiver of a full duplex communication system, where the transceiver includes a transmitter for transmitting a transmit signal and a receiver for receiving a receive signal, includes: an echo cancellation signal generator, coupled to the transmitter, for receiving the transmit signal and for generating an echo cancellation signal according to the transmit signal, wherein the echo cancellation signal reflects an effect of an impedance of a channel and a parasitic capacitor of the transceiver; and a calculation module coupled to the transmitter, the receiver, and the echo cancellation signal generator for receiving the receive signal and for canceling the echo of the receive signal according to the echo cancellation signal to generate an echo-cancelled signal, wherein the effect of the impedance of the channel and the parasitic capacitor of the transceiver in the echo-cancelled signal is reduced.

Abstract: An echo cancellation apparatus of a transceiver in a full duplex communication system is disclosed. The full duplex communication system includes a transmitter section for transmitting a transmit signal and a receiver section for receiving a receive signal. The echo cancellation device includes an echo cancellation signal generator coupled to the transmitter section for receiving the transmit signal and for generating an echo cancellation signal according to the transmit signal, a load resistor and a parasitic capacitor of the transceiver; and a calculation module coupled to the transmitter section, the receiver section, and the echo cancellation signal generator for receiving the receive signal and for eliminating at least high frequency components of the echo signal.

Abstract: A network device comprises a hybrid-mode transmitter for transmitting a differential transmission signal at a first transmission rate or a second transmission rate. The network device includes a first mode channel and a second mode channel. The first mode channel includes a voltage mode driver and a current mode driver for outputting the differential transmission signal. The second mode channel includes a second mode driver, which is one of a voltage mode driver and a current mode driver. The network device transmits the differential transmission signal at the first transmission rate through the voltage mode driver of the first mode channel and the second mode driver. The network device transmits the differential transmission signal at the second transmission rate through at least one of the current mode driver and the voltage mode driverfirst mode channel.

Abstract: The invention discloses a sink device and a signal receiving method thereof, applicable to wireless local area network. The sink device receives a plurality of beacon signals, synchronizes the beacon output signal generated by itself with the operating clock of the source device according to the above-mentioned timing synchronization data. And the sink device receives the plurality of beacon signals according to this calibrated synchronization clock.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A baseline wandering correction device for correcting baseline wandering of signals at a first output terminal and a second output terminal of a receiver includes: a control circuit for outputting a control signal according to voltages of the first and the second output terminals and a second threshold value; a voltage generation unit coupled to the control circuit for outputting a control voltage according to the control signal, the voltages of the first and the second output terminals, and a first threshold value; and a compensation current source coupled to the voltage generation unit for outputting a compensation current to the receiver according to the control voltage to correct the baseline wandering.

Abstract: The present invention discloses a digital-to-analog converter (DAC), including a bias voltage generating unit, a digital-to-analog converting stage, and an operating amplifier. The bias voltage generating unit is utilized for generating a first bias voltage. The digital-to-analog converting stage is utilized for converting a digital signal into a voltage signal, the digital-to-analog converting stage includes a current source for providing a current, and a switching unit is coupled to the current source for controlling the current to pass the switching unit according to the digital signal, and a load. The current flows through the load to generate the voltage signal. The operating amplifier is coupled to the bias voltage generating unit and the digital-to-analog converting stage for controlling the current source according to the first bias voltage.

Abstract: The present invention provides a communication apparatus. The communication apparatus includes a first processing circuit for processing data of a first network layer to generate a first parallel data; a parallel-to-serial converting unit coupled to the first processing circuit for generating a serial data according to the first parallel data generated by the first processing circuit; a transmitting interface coupled to the parallel-to-serial converting unit for transmitting the serial data generated by the parallel-to-serial converting unit; a serial-to-parallel converting unit coupled to the transmitting interface for converting the serial data transmitted by the transmitting interface into a second parallel data; and a second processing circuit for processing the second parallel data to generate data corresponding to a second network layer; wherein a transmitting frequency of the transmitting interface is different from operating frequencies of the first and the second processing circuit.

Abstract: The invention relates to an echo cancellation device for a full duplex communication system. The echo cancellation device utilizes a pull-up current source to increase the DC level, so as to improve the echo cancellation performance with avoiding signal distortion. And the pull-up current source used in the echo cancellation device can be implemented to a fixed current source or an adjustable current source.

Abstract: An echo cancellation device for a full duplex communications system is provided. The full duplex communication system has a transmitter for transmitting a transmit signal and a receiver for receiving a receive signal. The echo cancellation device has a filter for outputting a filter signal according to the transmit signal, an echo cancellation circuit connected to the filter for outputting an echo cancellation signal according to the filter signal, at least one echo cancellation resistor connected to the transmitter, the receiver, and the echo cancellation circuit, and an echo cancellation detection circuit for outputting a control signal according to an echo residue at the receiver to control the filter.

Abstract: A circuit for detecting phase errors and generating control signals includes a digital phase detector and a digital filter. The digital phase detector receives an input signal and a reference signal and generates a set of phase error control signals, and the digital filter receives the phase error control signals to generate control data. The digital filter can include a lookup table, an adder, and a register. The lookup table receives the phase error control signals and outputs a lookup value. The adder receives the lookup value and a register value and generates the control data. The register receives and stores the control data and outputs the stored control data as the register value.

Abstract: A stacked microphone jack assembly includes two identical microphone jacks each having a housing, which has a front plughole for receiving a microphone plug and two rows of vertical through holes, and conducting terminals each having a head extending to the inside of the housing for the contact of the plug of a microphone and a leg downwardly extending out of the bottom side of the housing, and a connector, which has a base sandwiched between the housings of the two microphone jacks, and a connection terminals respectively fastened to terminal slots on the base, each connection terminal having a clamping portion for clamping the legs of the conducting terminals of the overlying microphone jack respectively and a leg downwardly extending from the clamping portion and respectively inserted through the vertical through holes of the underlying microphone jack.

Abstract: A stacked microphone jack assembly includes two identical microphone jacks each having a housing, which has a front plughole for receiving a microphone plug and two rows of vertical through holes, and conducting terminals each having a head extending to the inside of the housing for the contact of the plug of a microphone and a leg downwardly extending out of the bottom side of the housing, and a connector, which has a base sandwiched between the housings of the two microphone jacks, and a connection terminals respectively fastened to terminal slots on the base, each connection terminal having a clamping portion for clamping the legs of the conducting terminals of the overlying microphone jack respectively and a leg downwardly extending from the clamping portion and respectively inserted through the vertical through holes of the underlying microphone jack.

Abstract: An electric connecting block for connecting two identical electric connectors together to form an AV connector is disclosed to include an electrically insulative block body with multiple terminal slots, and adapter terminals respectively mounted in the terminal slots for receiving connector terminals of one of the two electric connectors, each adapter terminal having a head with a retaining arm and a clamping arm positioned in one terminal slot for holding down one connector terminal of one of the two electric connectors and an terminal leg extending out of the bottom side of the block body for insertion through one insertion slot of the other of the two electric connectors.

Abstract: The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error ?e and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.