Abstract: A baseline wandering correction device for correcting baseline wandering of signals at a first output terminal and a second output terminal of a receiver includes: a control circuit for outputting a control signal according to voltages of the first and the second output terminals and a second threshold value; a voltage generation unit coupled to the control circuit for outputting a control voltage according to the control signal, the voltages of the first and the second output terminals, and a first threshold value; and a compensation current source coupled to the voltage generation unit for outputting a compensation current to the receiver according to the control voltage to correct the baseline wandering.

Abstract: The present invention discloses an interface circuit for a fiber transceiver, comprising: an encoder, for receiving and encoding an input data into an output differential signal; a comparator, for receiving an input differential signal from the fiber transceiver and generating an input signal; a decoder, for receiving the input signal and generating an encoded signal and an input data; and a detector, for receiving the encoded signal and generating a link signal supplied to the decoder to generate the input data.

Abstract: A multiple-phase switching circuit includes an alternative signal generator for generating a plurality of alternative signals according to a switching signal, and a multiplexer for receiving a plurality of clock signals and outputting a target clock signal according to the alternative signals. Only one of the alternative signals generated by the alternative signal generator is in a first logic level, while the other alternative signals are in a second logic level. The alternative signal generator changes the logic level of a first alternative signal having the first logic level into the second logic level, and changes the logic level of a second alternative signal adjacent to the first alternative signal into the first logic level.

Abstract: A driving circuit for a transceiver output port of a local area networking device is provided, including first and second current sources coupled to the ground, first and second resistors coupled to the supply voltage with the resistances of the first and second resistors each being equal to half that of the equivalent resistance of the cable for the purpose of impedance matching, and third and fourth current sources coupled to the cable for providing additional currents while the first and second current sources are operating such that the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.

Abstract: A digital to analog converter (DAC) converts a plurality of digital input data into a plurality of analog output signals. The DAC includes an element pool having a plurality of elements, a random number generator for converting the digital input data into a set of control signals, a plurality of summing nodes for generating analog output signals, and a plurality of switches for connecting the elements to the summing nodes. The switches are controlled by the control signals. Because of the control of the random number generator, the element signals transferring to the summing nodes can be used alternatively and simultaneously.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A circuit for detecting phase errors and generating control signals includes a digital phase detector and a digital filter. The digital phase detector receives an input signal and a reference signal and generates a set of phase error control signals, and the digital filter receives the phase error control signals to generate control data. The digital filter can include a lookup table, an adder, and a register. The lookup table receives the phase error control signals and outputs a lookup value. The adder receives the lookup value and a register value and generates the control data. The register receives and stores the control data and outputs the stored control data as the register value.

Abstract: A protection device disposed in a chip includes a decoding circuit for decoding a password and outputting a decoded signal, and a security circuit, coupled to the decoding circuit, for outputting an enable signal according to the decoded signal. The integrated circuit enables desired function of the chip according to the enable signal. Thus, the protection device can prevent the chip from being duplicated.

Abstract: A transceiver in a full duplex communication system includes a hybrid circuit for transmitting a transmission signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmission signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC is directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Abstract: A transmission line driver for generating an output signal to drive a transmission line is disclosed. The transmission line driver includes a voltage driver and a current driver. The voltage driver generates a voltage signal to drive the transmission line. The current driver generates a current signal to drive the transmission line. The amplitude of the output signal is determined according to the voltage signal and/or the current signal.

Abstract: A network interface includes a first network layer and a second network layer. The apparatus includes a first serial interface coupled to the first network layer and a second serial interface coupled to the second network layer. The first serial interface is for converting the first parallel data received from the first network layer into a first serial signal, and outputting the first serial signal serially. The second serial interface is for receiving and converting the first serial signal into the first parallel data, and sending the first parallel data to the second network layer.

Abstract: An echo cancellation apparatus of a transceiver in a full duplex communication system is disclosed. The full duplex communication system includes a transmitter section for transmitting a transmit signal and a receiver section for receiving a receive signal. The echo cancellation device includes an echo cancellation signal generator coupled to the transmitter section for receiving the transmit signal and for generating an echo cancellation signal according to the transmit signal, a load resistor and a parasitic capacitor of the transceiver; and a calculation module coupled to the transmitter section, the receiver section, and the echo cancellation signal generator for receiving the receive signal and for eliminating at least high frequency components of the echo signal.

Abstract: An echo cancellation device in a full duplex communication system having a transmitter for transferring an near-end signal and a receiver for receiving a far-end signal includes a filter for generating a filtered signal according to the near-end signal; an echo canceller coupled to the filter for generating an echo cancellation signal according to the filtered signal; and at least one echo cancellation resistor coupled to the transmitter, the receiver, and the echo canceller; wherein the echo canceller further includes a pull-up current source for increasing a DC level of the echo canceller.

Abstract: An echo cancellation device for a full duplex communications system is provided. The full duplex communication system has a transmitter for transmitting a transmit signal and a receiver for receiving a receive signal. The echo cancellation device has a filter for outputting a filter signal according to the transmit signal, an echo cancellation circuit connected to the filter for outputting an echo cancellation signal according to the filter signal, at least one echo cancellation resistor connected to the transmitter, the receiver, and the echo cancellation circuit, and an echo cancellation detection circuit for outputting a control signal according to an echo residue at the receiver to control the filter.

Abstract: A driving circuit for a transceiver output port of a local area networking device is provided, including first and second current sources coupled to the ground, first and second resistors coupled to the supply voltage with the resistances of the first and second resistors each being equal to half that of the equivalent resistance of the cable for the purpose of impedance matching, and third and fourth current sources coupled to the cable for providing additional currents while the first and second current sources are operating such that the magnitude of the differential output signal is determined not only according to the first and second currents but also according to the third and fourth currents.

Abstract: A network device comprises a hybrid-mode transmitter for transmitting a differential transmission signal at a first transmission rate or a second transmission rate. The network device includes a first mode channel and a second mode channel. The first mode channel includes a voltage mode driver and a current mode driver for outputting the differential transmission signal. The second mode channel includes a second mode driver, which is one of a voltage mode driver and a current mode driver. The network device transmits the differential transmission signal at the first transmission rate through the voltage mode driver of the first mode channel and the second mode driver. The network device transmits the differential transmission signal at the second transmission rate through at least one of the current mode driver and the voltage mode driverfirst mode channel.

Abstract: A multiple-phase switching circuit includes an alternative signal generator for generating a plurality of alternative signals according to a switching signal, and a multiplexer for receiving a plurality of clock signals and outputting a target clock signal according to the alternative signals. Only one of the alternative signals generated by the alternative signal generator is in a first logic level, while the other alternative signals are in a second logic level. The alternative signal generator changes the logic level of a first alternative signal having the first logic level into the second logic level, and changes the logic level of a second alternative signal adjacent to the first alternative signal into the first logic level.

Abstract: A digital to analog converter (DAC) converts a plurality of digital input data into a plurality of analog output signals. The DAC includes an element pool having a plurality of elements, a random number generator for converting the digital input data into a set of control signals, a plurality of summing nodes for generating analog output signals, and a plurality of switches for connecting the elements to the summing nodes. The switches are controlled by the control signals. Because of the control of the random number generator, the element signals transferring to the summing nodes can be used alternatively and simultaneously.

Abstract: The present invention is to provide a multiple phases switching circuit which is operable with a multiple phase signal generator and a succeeding circuit. The multiple-phase signal generator generates N multiple-phase clock signals. Phases of the multiple-phase clock signals are different. The multiple phases switching circuit comprises an alternative signal generator and a multiplexer. The alternative signal generator outputs an alternative signal according to an up/down switching signal. The multiplexer is coupled to the alternative signal generator for receiving the multiple-phase clock signals and proceeding a glitch/spike preventing process according to the alternative signal so as to output a target clock signal to the succeeding circuit.

Abstract: A circuit for a transceiver output port of a local area networking device is provided and includes a first and a second current source coupled to the ground, a first and a second resistor coupled to the supply voltage, wherein the resistances of the first and the second resistors each are equal to half that of the equivalent resistance of the UTP cable for the purpose of impedance matching, and a third current source and a fourth current source coupled to the UTP cable for providing additional current for the circuit. The magnitude of the differential signal output from the circuit can thus sustain in a predetermined range even if the magnitude of the supply voltage is lower than the minimum magnitude required by the conventional circuit.