Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: The present invention discloses an interface circuit for a fiber transceiver, comprising: an encoder, for receiving and encoding an input data into an output differential signal; a comparator, for receiving an input differential signal from the fiber transceiver and generating an input signal; a decoder, for receiving the input signal and generating an encoded signal and an input data; and a detector, for receiving the encoded signal and generating a link signal supplied to the decoder to generate the input data.

Abstract: The present invention is to provide a multiple phases switching circuit, which can be used in a multiple phase signal generator and a succeeding circuit, in the same time, the multiple phase signal generator will generate N multiple phases clock signals that spreading 360 degrees, the phase of any clock signal is ahead of the phase of the next coming clock signal, the multiple phase switching circuit comprises:

Abstract: The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error &thgr;e and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A device and method for correcting the baseline wandering of transmitting signals are disclosed. The present method and device are used to correct the baseline wandering of the first output terminal and the second output terminal of a receiver as a result of induction effect of the transformer. The present device comprises a compensation current source including a first compensation output terminal and a second compensation output terminal which are respectively connected to the first output terminal and the second output terminal of the receiver. The device further includes a voltage signal generator for generating a control voltage to control the compensation current source. The voltage signal generator employs the voltage difference of the first output terminal and the second output terminal of the receiver and a reference voltage to control the control voltage.

Abstract: The present invention provides a phase detector without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter. It can output a plurality of control signals (up,dn) through the function of a plurality of multi-phase clock signals to detect the transition edge of data signals. Therefore, the relation between the phase error &thgr;e and the voltage Vd of a phase-locked loop can be adjusted to be nearly linear dependent. In this way, the phase-locked loop in accordance with the present invention has no dead zone, clock jitter can be reduced and tolerance for data random jitter can be enhanced.

Abstract: A phase-locked loop which is characterized by using two identical phase shifters and programmable UP/DN counters to generate a timing clock having accurate frequency. The clock which is used to recover the received data is made synchronous with the data by adjusting its phase without affecting its frequency. Therefore, frequency drift caused by data jitter of received data does not occur in the phase-locked loop according to the present invention. Besides, since the invention is an all-digital circuit, it is not sensitive to temperature change, voltage variation, or fabricating process fluctuation. Furthermore, it has excellent noise immunity.

Abstract: A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.