Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

Abstract: Disclosed herein, inter alia, are compounds, compositions, and methods of use thereof in the sequencing of a nucleic acid.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.

Abstract: A gate drive circuit includes a plurality of gate drive units. Each of the gate drive units includes a stage transmission signal selection circuit, a pull-up control circuit, a pulse number reduction circuit, a first inversion circuit, a first output stage, and a second output stage, and can output a second gate control signal with a greater number of pulses and a first gate control signal with a less number of pulses. At least one of the stage transmission signal selection circuit, the first inversion circuit or the second output stage includes three transistors with the same channel type.

Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Abstract: A dust-proof telecommunication system is disclosed. The dust-proof telecommunication system includes a chassis, critical components located within the chassis, and a filter module located within the chassis near at least some of the critical components that need to be cooled. For example, the critical components include a central processing unit (CPU), a system on chip (SoC), a memory module, a PCIe card, and/or a chipset. The filter module has a filter cover that surrounds at least in part the critical components, a first air filter located at an inlet of an airflow, and a second air filter located at an outlet. The critical components located at a protective space within the chassis receive and are cooled by the airflow passing through the air filter.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.

Abstract: Embodiments of this application provide example methods for accessing a core network by using a fixed access device. One example method includes: receiving, a network registration request sent by customer-premises equipment; sending a network registration request message for the CPE to a mobile core network based on the network registration request; receiving an authentication request message; performing physical location authentication for the CPE based on a physical location identifier; in response to determining that the physical location authentication succeeds, sending an authentication response to the mobile core network; receiving a registration success message sent by the mobile core network; notifying, based on the registration success message, the CPE that network registration succeeds; and sending a service parameter to the CPE.

Abstract: A circular polarized antenna array module and a wireless communication device, including a plurality of circular polarized transmitting antennas and circular polarized receiving antennas, a dielectric substrate, and a plurality of first group of phase shifting units and second group of phase shifting units. In each row of the circular polarized transmitting/receiving antennas, every two adjacent circular polarized transmitting/receiving antennas arranged with a distance, each of the circular polarized transmitting antennas arranged with a first feed point and a second feed point, each of the circular polarized receiving antennas arranged with a third feed point and a fourth feed point. Each row of the circular polarized transmitting antennas and each row of the circular polarized receiving antennas alternately placed to form array arranged on the dielectric substrate.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.

Abstract: Image sensors and methods for forming the same are provided. A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.

Abstract: A method for treating bedsores is provided, including administering a pharmaceutical composition includes an effective amount of mangosteen fruit shell extract to a subject suffering from bedsores, wherein the mangosteen fruit shell is outer shell of the mangosteen fruit shell and/or inner shell of the mangosteen fruit shell, and wherein the pharmaceutical composition is an external preparation.

Abstract: Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.

Abstract: Disclosed are a document processing device and a signal transmission method thereof. The document processing device includes a processor and a printing engine. The processor is connected to the printing engine. The processor receives a document output command to generate a first differential signal. Then, the printing engine receives the first differential signal and converts the first differential signal into a first interference-free information packet. When the printing engine has already obtained the first interference-free information packet, the printing engine sends a buffer status checking signal to the processor. The document processing device uses the transmission of the first differential signal to reduce printing information errors caused by static interference, so as to achieve the purpose of improving the accuracy of printing information.

Abstract: In example implementations, an apparatus is provided. The apparatus includes an interface, an integrated graphical processing unit (GPU), a discrete GPU, and a controller. The interface is to receive a connection to an external display device. The integrated GPU and the discrete GPU are communicatively coupled to the interface. The controller is communicatively coupled to the integrated GPU and the discrete GPU and is to deactivate the discrete GPU and activate the integrated GPU in response to detection of the external display device connected to the interface.