Abstract: A battery module includes a battery cell assembly and a fire extinguishing member. The battery cell assembly includes a plurality of battery cell frames and a plurality of battery cells. The plurality of the battery cell frames are arranged sequentially along a length direction of the battery module. At least one battery cell is provided in at least some of the battery cell frames. Each battery cell frame is provided with a fire extinguishing slot, and the fire extinguishing slots on the plurality of the battery cell frames are communicated to each other to form a fire extinguishing channel. The fire extinguishing member is arranged in the fire extinguishing channel. The fire extinguishing channel extends along the length direction of the battery module, and the fire extinguishing member extends along the length direction of the battery module in the fire extinguishing channel.

Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

Abstract: The disclosure discloses a penetrating cushion damping device comprising a penetrator, and belongs to the field of in-situ penetrating exploration of extraterrestrial celestial bodies. A magnetic conductor encloses the non-penetrating end of the penetrator, a drag plate connected to the penetrator is provided at the lower end face of the magnetic conductor, and a magnetic source structure for generating magnetic force on the magnetic conductor is provided in the non-penetrating end of the penetrator. The disclosure utilizes the penetrating cushion anti-drag mode with the drag plate and the electromagnetic structure, which is self-adaptive to the flight penetration speed and compact in structure, reduces the jump probability, and further reduces the cushion resistance after the speed is reduced.

Abstract: This disclosure is directed to a liquid cooling device having at least two collecting tanks and at least one pair of heat-exchange plates. The tanks are separated from each other. Each of the collecting tanks has a joint tube. Each of the heat-exchange plates is in elongated shape and the collecting tanks are connected serially by the heat-exchange plates. The two collecting tanks are connected by the pair of heat-exchange plates. Each of the heat-exchange plates has a channel extended along the longitudinal direction thereof. The channels in the heat-exchange plates are connected to the collecting tanks at two ends of the heat-exchange plates, respectively. The longitudinal directions of the channels of the heat-exchange plates between the collecting tanks are parallel to each other.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, the first portion is between the neck portion and the conductive pad, and the neck portion is narrower than both of the first portion and the second portion. The chip structure includes a support layer over the second portion of the conductive bump. A first composition of the support layer is different from a second composition of the conductive bump. The chip structure includes a solder structure over the support layer.

Abstract: The present disclosure discloses an expectorant compound, and specifically discloses compounds represented by formula I and formula II, pharmaceutically acceptable salts or tautomers thereof.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.

Abstract: A resource integration method includes the following steps: a receiving module receives access information from a guest operating system on the host device; the access information is used to determine whether the frame rate is lower than a frame rate threshold; when the receiving module determines that the frame rate is lower than the frame rate threshold, the receiving module transmits an external resource request signal to the receiving module; after the receiving module receives the external resource request signal, a resource management module (which is located in the bridge module) selects an optimal external device from a specific category (among a plurality of categories in a candidate list), and a calculation operation or a storage operation corresponding to the specific category is transmitted to the optimal external device for calculation or storage by the bridge module.

Abstract: The present invention provides a voltage control method for controlling a power supply. The voltage control method comprises the following steps: obtaining a present output voltage value associated with a present gain value; obtaining a predetermined output voltage value associated with a predetermined duty ratio; calculating a target gain value, corresponding to the predetermined duty ratio, according to a gain value formula; performing a weight calculation on the present gain value and the target gain value for generating a buffer gain value; and setting an output voltage command according to the buffer gain value. Wherein the buffer gain value is between the present gain value and the target gain value.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Abstract: Stevia varieties with high a content of RebD, a high content of RebM, and a high content of RebD and RebM containing various SNP markers and UGT isoforms, are disclosed. Methods of screening for the SNPs are also disclosed as well as for using the SNPs in marker assisted breeding. Further provided are methods for introgressing the disclosed SNPs associated with high RebD and high RebM into Stevia plants by selecting plants comprising for one or more SNPs and breeding with such plants to confer such desirable agronomic phenotypes to plant progeny.

Abstract: An imaging lens assembly has an optical axis and includes an annular structure located on an object side of the imaging lens assembly and surrounds the optical axis. The annular structure is located on an object side of the imaging lens assembly, surrounds the optical axis, and includes a first through hole, a second through hole, a first frustum surface, a second frustum surface and a third frustum surface. The first through hole is disposed on an object side of the annular structure, and the second through hole is disposed on an image side of the first through hole. The first frustum surface is disposed on the image side of the first through hole. The second frustum surface is disposed on an object side of the second through hole. The third frustum surface is disposed on an image side of the second through hole.

Abstract: An accuracy measurement method of an autonomous mobile vehicle, a calculating device, and an autonomous mobile vehicle are provided. The accuracy measurement method includes a distance calculating step, a regression center calculating step, and an average calculating step. The distance calculating step includes a controlling step, a light beam emitting step, an image capturing step, an image analyzing step, and a converting step. The regression center calculating step is performed after the distance calculating step is repeatedly performed by at least two times. The accuracy measurement method is performed to obtain an X-axis offset in an X-axis direction, a Y-axis offset in a Y-axis direction, and an angle deflection of an autonomous mobile vehicle.

Abstract: An approach is disclosed that receives an incoming data record, the data record including a number of data fields. The approach determines a current Real-Time Resources Score (RTRS). The RTRS being a forecast of the information handling system's ability to handle incoming data transmissions. When the RTRS is lower than a current data accumulation rate, a subset of the data record is sent based on field priorities. The approach assigns priorities to each of the data fields included in the data record based on a priority assessment of the respective data fields. The approach then sends, to a data receiver, a subset of the plurality of data fields based on the assigned priority.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.

Abstract: In a method of manufacturing a semiconductor device, an n-type source/drain epitaxial layer and a p-type source/drain epitaxial layer respectively formed, a dielectric layer is formed over the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer, a first opening is formed in the dielectric layer to expose a part of the n-type source/drain epitaxial layer and a second opening is formed in the dielectric layer to expose a part of the p-type source/drain epitaxial layer, and the n-type source/drain epitaxial layer and the p-type source/drain epitaxial layer respectively recessed. A recessing amount of the n-type source/drain epitaxial layer is different from a recessing amount of the p-type source/drain epitaxial layer.