Abstract: A three-dimensional stacked semiconductor package device includes first and second semiconductor package devices and a conductive bond. The first device includes a first insulative housing, a first semiconductor chip and a first lead that is bent outside the first insulative housing. The second device includes a second insulative housing, a second semiconductor chip and a second lead that is flat outside the second insulative housing. The conductive bond contacts and electrically connects the leads.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a metal filler, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line is contiguous with and integral with the bumped terminal and extends laterally beyond the bumped terminal and the metal filler, and the metal filler contacts the bumped terminal in a cavity that extends through the bumped terminal.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a metal pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line is contiguous with the bumped terminal and extends laterally beyond the bumped terminal and the metal pillar, and the metal pillar contacts and extends vertically beyond the bumped terminal.

Abstract: A method of making a three-dimensional stacked semiconductor package includes providing a first semiconductor chip assembly that includes a first chip, a first conductive trace and a first encapsulant, wherein the first conductive trace includes a first metal pillar, providing a second semiconductor chip assembly that includes a second chip, a second conductive trace and a second encapsulant, wherein the second encapsulant includes a second aperture, and then positioning the first and second assemblies such that the first assembly overlaps the second assembly and the first metal pillar extends into the second aperture.

Abstract: A method of making a semiconductor chip assembly includes providing a metal base, a routing line and a bumped terminal, then mechanically attaching a semiconductor chip to the metal base, the routing line and the bumped terminal, then forming an encapsulant, and then etching the metal base to form a metal pillar that contacts the bumped terminal.

Abstract: A method of making a semiconductor chip assembly includes providing a metal base, a routing line, a bumped terminal and a metal filler, then mechanically attaching a semiconductor chip to the metal base, the routing line, the bumped terminal and the metal filler, then forming an encapsulant, then etching the metal base to expose the bumped terminal, and then grinding the bumped terminal to expose the metal filler.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies. The first semiconductor chip assembly includes a first chip, a first conductive trace and a first encapsulant, and the first conductive trace includes a first metal pillar. The second semiconductor chip assembly includes a second chip, a second conductive trace and a second encapsulant, and the second encapsulant includes a second aperture. The first metal pillar extends into the second aperture.

Abstract: A method of making a semiconductor chip assembly includes mechanically attaching a semiconductor chip that includes a conductive pad to a routing line, mechanically attaching and electrically connecting a metal particle to the routing line, wherein the routing line extends laterally beyond the metal particle towards the chip and the chip and the metal particle extend vertically beyond the routing line in the same direction, forming an encapsulant after attaching the chip and the metal particle to the routing line wherein the chip and the metal particle are embedded in the encapsulant, and forming a connection joint that electrically connects the routing line and the pad.

Abstract: A semiconductor package device includes an insulative housing, a semiconductor chip, and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the bottom surface includes a peripheral portion and a central portion within the peripheral portion, the peripheral portion protrudes downwardly from the central portion, the chip includes a conductive pad, and the lead protrudes laterally from and extends through the peripheral side surface and is electrically connected to the pad.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a metal particle, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line extends laterally beyond the metal particle towards the chip, and the chip and the metal particle are embedded in the encapsulant and extend vertically beyond the routing line in the same direction.

Abstract: A method of making a semiconductor package device includes providing a conductive trace that includes a terminal and a lead, wherein the terminal and the lead are electrically connected to one another, attaching the conductive trace to a semiconductor chip using an insulative adhesive, wherein the chip includes a conductive pad, forming a first insulative housing portion that contacts the chip and the lead without contacting the terminal, wherein the lead protrudes laterally from and extends through the first insulative housing portion, forming a connection joint that contacts and electrically connects the conductive trace and the pad, and forming a second insulative housing portion that contacts the adhesive, the terminal and the first insulative housing portion after forming the first insulative housing portion, wherein the terminal protrudes downwardly from and extends through the second insulative housing portion, and the first and second insulative housing portions form an insulative housing that surroun

Abstract: A semiconductor package device includes an insulative housing, a semiconductor chip and a conductive trace, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the conductive trace includes a routing line, a terminal and a lead, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.

Abstract: A method of making a semiconductor package device includes providing an insulative housing, a semiconductor chip, a terminal and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the terminal protrudes downwardly from and extends through the bottom surface, the lead protrudes laterally from and extends through the side surface, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal is electrically connected to the lead and the pad inside the insulative housing and outside the chip, singulating the lead from a lead frame, and trimming the lead without trimming the terminal.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a metal base, an insulative base, a routing line and an interconnect, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the routing line is disposed on a side of the insulative base that faces towards the chip, and the interconnect extends through a via in the insulative base and electrically connects the metal base and the routing line, forming an opening that extends through the insulative base and exposes the pad, forming a connection joint that electrically connects the routing line and the pad, and etching the metal base such that an unetched portion of the metal base forms a pillar that overlaps and is aligned with the via and contacts the interconnect, wherein a conductive trace includes the routing line, the interconnect and the pillar.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, the conductive trace includes a contact terminal that extends through the insulative base, and the pad is exposed through an opening that extends through the metal base and the insulative base and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

Abstract: A method of making an optoelectronic semiconductor package device includes attaching a conductive trace to a semiconductor chip using a transparent adhesive, wherein the chip includes an upper surface and a lower surface, and the upper surface includes a light sensitive cell and a conductive pad, then forming an encapsulant that covers the lower surface, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A method of making a semiconductor package device includes attaching a semiconductor chip to a metallic structure using an insulative adhesive, wherein the chip includes a conductive pad, the metallic structure includes first and second opposing surfaces and a lead, the adhesive is disposed between the first surface and the chip, the lead includes a recessed portion, a non-recessed portion and opposing outer edges between the first and second surfaces that extend across the recessed and non-recessed portions, and the recessed portion is recessed relative to the non-recessed portion at the second surface, forming an encapsulant that contacts the chip, the first surface, the outer edges and the recessed portion, wherein the encapsulant completely covers the chip, the outer edges and the recessed portion without completely covering the non-recessed portion, and forming a connection joint that electrically connects the lead and the pad.

Abstract: A semiconductor package device includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another inside the insulative housing and outside the chip.

Abstract: A test probe includes a conductive trace with a bumped terminal, the bumped terminal includes a jagged contact surface and a cavity that face in opposite directions, and the contact surface includes a plated metal. The contact surface is jagged due to particles which may protrude, be covered or dislodged. Preferably, the test probe includes an elastomer that fills the cavity so that the bumped terminal is compliant. The test probe is well-suited for pressure contact with semiconductor chips, BGA packages and other electronic devices.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.