Abstract: An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the insulative housing includes a first single-piece non-transparent insulative housing portion that contacts the lower surface and is spaced from the light sensitive cell and a second transparent insulative housing portion that contacts the first housing portion and the light sensitive cell, and the conductive trace extends outside the insulative housing and is electrically connected to the pad inside the insulative housing.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip and a laminated structure, wherein the chip includes a conductive pad, the laminated structure includes a conductive trace, an insulative base and a metal base, the conductive trace includes a routing line and a bumped terminal, the metal base and the routing line are disposed on opposite sides of the insulative base, and the bumped terminal includes a cavity that extends through the insulative base and into the metal base, removing a portion of the metal base that contacts the bumped terminal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, the pillars are disposed outside the peripheries of the chips and aligned with one another, and the first pillar extends into a cavity in the second pillar. The conductive bond is within the cavity and contacts and electrically connects the pillars.

Abstract: A method of testing a semiconductor package device includes providing a device that includes an insulative housing, a semiconductor chip, a terminal and a lead, wherein the terminal protrudes downwardly from and extends through a bottom surface of the housing, the lead protrudes laterally from and extends through a side surface of the housing, and the terminal and the lead are electrically connected to one another and a chip pad inside the housing, attaching the device to a test socket that electrically contacts the lead without electrically contacting the terminal, testing the test socket, and removing the device from the test socket. The method may include trimming the lead after removing the device from the test socket and the attaching the device to a printed circuit board that electrically contacts the terminal without electrically contacting the lead.

Abstract: A multichip semiconductor package device includes first and second devices and a conductive bond. The first device includes an insulative housing, a first semiconductor chip and a conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The conductive trace includes a terminal that extends through the central portion and a lead that protrudes laterally from and extends through the side surface. The second device includes a second semiconductor chip, extends into the cavity and is positioned within and does not extend outside a periphery of the cavity. The conductive bond is inside the cavity, on the terminal and contacts and electrically connects the first and second devices.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip that includes a conductive pad, providing a conductive trace and a metal base, wherein the conductive trace includes a routing line and a contact terminal, the routing line is disposed outside the metal base, the contact terminal extends from the routing line through the metal base, the contact terminal includes a plated metal that contacts and extends through the metal base, the plated metal forms a peripheral sidewall portion of the contact terminal, and the plated metal surrounds a central surface area without extending into the central surface area, then mechanically attaching the chip to the conductive trace, removing a portion of the metal base that contacts the plated metal, and forming a connection joint that contacts and electrically connects the conductive trace and the pad.

Abstract: A three-dimensional stacked semiconductor package device includes first and second semiconductor package devices and a conductive bond. The first device includes a first insulative housing, a first semiconductor chip and a first conductive trace. The first insulative housing includes a peripheral ledge and a central portion that is recessed relative to the peripheral ledge, and the peripheral ledge and the central portion form a cavity. The first conductive trace includes a first terminal that extends through the central portion. The second device includes a second insulative housing, a second semiconductor chip and a second conductive trace. The second insulative housing includes a second bottom surface. The second conductive trace includes a second terminal that extends through the second bottom surface. The conductive bond contacts and electrically connects the terminals, and the second terminal extends into the cavity.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip with upper and lower surfaces, wherein the upper surface includes a conductive pad, providing a conductive trace, then disposing an insulative adhesive between the conductive trace and the chip, thereby mechanically attaching the conductive trace to the chip such that the conductive trace overlaps the pad, the adhesive contacts and is sandwiched between the conductive trace and the pad, and the conductive trace and the pad are electrically isolated from one another, then removing the adhesive between the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the adhesive is removed by laser ablation then plasma etching.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the bumped terminal includes a cavity that extends through the insulative base, and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, an insulative adhesive that attaches the chip to the conductive trace or an encapsulant that encapsulates the chip fills the cavity and provides compressible mechanical support for the bumped terminal.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

Abstract: A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a conductive trace, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, and the conductive trace includes a contact terminal that extends through the insulative base, then forming an opening that extends through the metal base and the insulative base, exposes the pad and is spaced from the contact terminal, then forming a connection joint that contacts and electrically connects the conductive trace and the pad, and then removing a portion of the metal base that contacts the contact terminal. Preferably, the opening extends through an insulative adhesive that attaches the chip to the conductive trace.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the base includes a recess, the conductive trace is disposed proximate to the pad, the base contacts and covers the conductive trace on a side opposite the chip, the bumped terminal is in the recess, and the conductive trace and the base are different metals, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is outside a periphery of the chip, and an encapsulant provides compressible mechanical support for the bumped terminal.

Abstract: A method of connecting a conductive trace to a semiconductor chip includes providing a semiconductor chip, a conductive trace and a base, wherein the chip includes a conductive pad, the base includes a recess, the conductive trace includes a bumped terminal in the recess, the bumped terminal includes a cavity that extends into and faces away from the recess, the base contacts and covers the conductive trace on a side opposite the chip, and the conductive trace and the base are different metals, mechanically attaching the chip to the conductive trace using an insulative adhesive that extends into the cavity, etching the base to expose the conductive trace, and forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, the bumped terminal is inside a periphery of the chip, and the adhesive fills the cavity.

Abstract: A semiconductor module includes a first semiconductor chip assembly, a second semiconductor chip assembly, an encapsulant base and an electrical interconnect. The first assembly includes a first semiconductor chip, a first conductive trace and a first connection joint, the first chip includes a first conductive pad, the first trace extends within and outside a periphery of the first chip, and the first connection joint contacts and electrically connects the first trace and the first pad. The second assembly includes a second semiconductor chip, a second conductive trace and a second connection joint, the second chip includes a second conductive pad, the second trace extends within and outside a periphery of the second chip, and the second connection joint contacts and electrically connects the second trace and the second pad. The encapsulant base is disposed between and in contact with the first and second chips and the first and second traces.

Abstract: The present invention provides a leadframe package formed by flip chip on leadframe technique. The chips are face to face attached on both sides of the leadframe surface. Another embodiment according to the present invention is that the chips are back to back attached on a leadframe. A chip with smaller size is stacked on a further chip with larger size. The smaller chip is connected to the leadframe by wire bonding. The present invention includes a first chip attached on the leadframe by using flip chip technology. The first chip has a plurality of conductive bump for electrically transferring signal to external. The tape has a plurality of openings or slots through the tape. Each opening exposes the terminal of the inner leads. Thus, a further chip can be set on the opposite major surface of the leadframe by means of the openings or slots. The second chip can be optionally face to face formed on the other side of the leadframe or back to back stacked on the first chip.

Abstract: A testing means for holding chips to perform tests comprises of a plurality of inner leads for providing electrical connection for the chips with a plurality of conductive bumps. A metal layer is formed on surfaces of the plurality of inner leads for fixing the chips on the plurality of inner leads, wherein a melting point of the metal layer is below a melting point of the conductive bumps. Then, a adhesive material is pasted on a bottom surface of the plurality of inner leads for fixing the plurality of inner leads. A holding means is used to connect and hold the plurality of inner leads, and used for providing electrical connection for the plurality of inner leads.

Abstract: In accordance with the present invention, a test board for connecting a bare die to a leadframe for testing the die is provided. The test board has a conducting surface on a bottom portion of the board that is adapted to engage and electrically connect to a lead finger in the leadframe. A tape automated bonding tape which has a conductive lead and a first and a second conductive bump are provided where the first conductive bump is situated on an upper surface of the lead and the second conductive bump is situated on a bottom surface of the lead. The first and second conductive bumps establish an electrical communication between the bumps throughout the conductive lead. The first conductive bump is also connected to the conducting surface of the board and the second bump is adapted to engage in I/O pad so that the bare die may be tested through the leadframe.

Abstract: The semiconductor package for improving the efficiency of spreading heat and the capability of electrical function is disclosed. A semiconductor die is attached on the BT substrate by using a conventional die attaching material. The die is electrically coupled to conductive traces on the top surface of the substrate by the bonding wires, a TAB method or a flip chip method. A plurality of conductive vias are also need for electrically coupling conductive traces on the top surface of the substrate to those on the bottom. At an end portion of each conductive trace on the bottom of the substrate is an conductive pad for connecting to a solder ball for transferring electrical signal. A heatspreader is exactly set over the semiconductor die for improve the efficiency of spreading heat. Additionally, the heatspreader is connected on the ground land of the substrate via a conductive adhesives to form a ground plane.

Abstract: A method is devised for packaging semiconductor chips based on a lead-on-chip (LOC) architecture which allows the size of the package to be substantially close to the chip size so as to reduce the packaging size to the minimum. The semiconductor chip is mounted based on a lead-on-chip architecture on a leadframe having a plurality of leads, a side rail, and at least a first connecting piece and a second connecting piece. In this method, the first step is to attach a ring to the leadframe. Then, the semiconductor chip is mounted on the leadframe and a plurality of wires are interconnected between the bonding pads on the semiconductor chip and the leads on leadframe. After that, a liquid epoxy is applied to the semiconductor chip so as to form a molding compound encapsulating the semiconductor chip. Finally, the side rail of the leadframe is removed from the leadframe. The step of encapsulation can be implemented either by epoxy dispensing or by print encapsulation system (PES).

Abstract: A method of detachably mounting a heat sink to a lead frame and then an IC die to the heat sink including the steps of first providing a lead frame that has lead fingers and a multiplicity of tie bars extending inwardly from the lead frame, each tie bar has a fixed end integral with the lead frame and a free end equipped with an attachment means, and then providing a heat sink that has a multiplicity of receptacle means adapted to receive the attachment means on the tie bars as well as at least one opening through the thickness of the heat sink, and detachably engaging the attachment means on the tie bars to the receptacle means on the heat sink. The invention is also directed to a lead frame/heat sink assembly that may have a single IC die or a multiple of IC dies mounted on top of the heat sink. A single IC die or a multiple of IC dies that are mounted to the heat sink can be tested in a KGD or KGS test before being assembled to a lead frame.