Patents by Inventor Cheng Liu

Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929871
    Abstract: The present disclosure provides a method for generating a backbone network, an apparatus for generating a backbone network, a device, and a storage medium. The method includes: acquiring a set of a training image, a set of an inference image, and a set of an initial backbone network; training and inferring, for each initial backbone network in the set of the initial backbone network, the initial backbone network by using the set of the training image and the set of the inference image, to obtain an inference time and an inference accuracy of a trained backbone network in an inference process; determining a basic backbone network based on the inference time and the inference accuracy of the trained backbone network in the inference process; and obtaining a target backbone network based on the basic backbone network and a preset target network.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 12, 2024
    Inventors: Cheng Cui, Tingquan Gao, Shengyu Wei, Yuning Du, Ruoyu Guo, Bin Lu, Ying Zhou, Xueying Lyu, Qiwen Liu, Xiaoguang Hu, Dianhai Yu, Yanjun Ma
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240076370
    Abstract: The presently disclosed subject matter provides antibodies that bind to GPRC5D and methods of using the same.
    Type: Application
    Filed: December 22, 2022
    Publication date: March 7, 2024
    Applicants: MEMORIAL SLOAN-KETTERING CANCER CENTER, EUREKA THERAPEUTICS, INC.
    Inventors: Renier J. Brentjens, Eric L. Smith, Cheng Liu
  • Publication number: 20240078653
    Abstract: A visual inspection method of a curved object executed by a visual inspection system. The visual inspection system includes a robotic arm, a camera mounted at a tail end of the robotic arm, a fixing unit mounted under the camera, and a control unit electrically connected to the robotic arm and the camera. Specific steps of the visual inspection method of the curved object are described hereinafter. Fix a curved object which is to be inspected by the fixing unit. Capture the object which is to be inspected with a plurality of groups of preset parameters by the camera. Use the control unit to calculate a better shooting parameter. Use the better shooting parameter by the camera to proceed with visual inspections of the curved objects which are to be inspected in batches.
    Type: Application
    Filed: June 21, 2023
    Publication date: March 7, 2024
    Inventors: SHUN-CHIEN LAN, WEI-CHENG TSENG, CHEN-YI LIU, CHEN-TE CHEN
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240074826
    Abstract: A surgical robot including at least one contact module, a control connection module, at least one first robotic arm, and at least one grip control device. A first transmission member of the control connection module drives the control module through a first transmission connecting member. A first shaft member of the first robotic arm is connected with the first transmission member while the grip control device is connected with the first robotic arm by a transmission interface. A force sensing member of the first robotic arm detects a first reaction force from the contact module so that the first robotic arm sends a feedback control signal to the grip control device to control a grip driving member to generate a force feedback for allowing a grip portion to move. Thereby, users can feel movement of the grip portion caused by the force feedback to avoid accidental iatrogenic injuries.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 7, 2024
    Inventors: PO-YUN LIU, CHUN-HUNG KUO, CHIH-CHENG CHIEN, YEN-CHIEH WANG
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
  • Patent number: 11923432
    Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
  • Patent number: 11919247
    Abstract: A powder-based three-dimensional printing (3DP) method, device and system, and a computer-readable storage medium. The method includes: analyzing printing images of layers corresponding to a part to be printed to determine a target print image and adding a preset mark to the target print image which includes a print image of a target layer that causes a previous powder layer of the target layer to displace during printing; acquiring an image to be printed of a current layer to be printed; identifying the image to be printed to determine whether the preset mark exists on the image to be printed; and if yes, processing the current layer to be printed and/or a previous powder layer of the current layer to be printed such that the previous powder layer of the current layer does not move with powder spreading of the current layer.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: March 5, 2024
    Assignee: KOCEL INTELLIGENT MACHINERY LIMITED
    Inventors: Fan Peng, Donge Zheng, Yinxue Du, Yi Liu, Jun Yang, Cheng Hu, Zixiang Zhou
  • Patent number: 11924965
    Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Jian-Hong Lin, Shu-Yuan Ku, Wei-Cheng Liu, Yinlung Lu, Jun He
  • Patent number: 11923688
    Abstract: An exemplary two-step method for power system inertia online estimation is described. The first step is to accurately estimate the POI-level aggregated inertia. The second step is to calculate the system-level inertia constant by weighting all the POI-level aggregated inertia and to monitor the inertia spatial distribution. In one example embodiment, the PMU is installed at POI, the frequency spatial difference is considered, and the mechanical power is carefully treated.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: March 5, 2024
    Assignee: NORTH CHINA ELECTRIC POWER UNIVERSITY
    Inventors: Tianshu Bi, Cheng Wang, Jiahao Liu, Guoyi Xu
  • Publication number: 20240071814
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Publication number: 20240071776
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU
  • Publication number: 20240074068
    Abstract: An electronic device includes a back board, a circuit board, a first attaching member and a second attaching member. The circuit board is arranged on the back board. The first attaching member is arranged between the back board and the circuit board. The second attaching member is arranged between the back board and the circuit board. The circuit board is fixed on the back board through the first attaching member and the second attaching member, and a material of the first attaching member is different from that of the second attaching member.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 29, 2024
    Inventors: Yuan-Cheng LIU, Meng-Syuan WU, Hsin-Cheng CHEN
  • Publication number: 20240071731
    Abstract: A substrate processing apparatus, comprising: a processing chamber having a plasma intake wall configured to receive plasma from a remote plasma source (RPS) and a surrounding wall having an inner surface defining an interior volume for receiving a substrate; and a substrate support having a substrate supporting surface facing the plasma intake wall and elevatably arranged in the interior volume of the processing chamber. The surrounding wall, in a cross-section of the processing chamber, includes: a first segment having a first width associated with a processing region for the substrate support; a second segment having a width greater than the first width that is further away from the plasma intake wall than the first segment.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Inventors: Yi-Yuan HUANG, Yi-Cheng LIU
  • Publication number: 20240074328
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240071451
    Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
    Type: Application
    Filed: January 21, 2021
    Publication date: February 29, 2024
    Inventors: Huai LIN, Guozhong XING, Zuheng WU, Long LIU, Di WANG, Cheng LU, Peiwen ZHANG, Changqing XIE, Ling LI, Ming LIU
  • Publication number: 20240074282
    Abstract: The present application provides a displaying base plate and a displaying device, which relates to the technical field of displaying. The displaying device can ameliorate the problem of screen greening caused by electrostatic charges, thereby improving the effect of displaying. The displaying base plate includes an active area and a non-active area connected to the active area, the non-active area includes an edge region and a first-dam region, and the first-dam region is located between the active area and the edge region; the displaying base plate further includes: a substrate; an anti-static layer disposed on the substrate, wherein the anti-static layer is located at least within the edge region; and a driving unit and a touch unit that are disposed on the substrate, wherein the driving unit is located within the active area.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yu Zhao, Yong Zhuo, Wei He, Yanxia Xin, Qun Ma, Xiping Li, Jianpeng Liu, Kui Fang, Cheng Tan, Xueping Li, Yihao Wu, Xiaoyun Wang, Haibo Li, Xiaoyan Yang
  • Patent number: 11917230
    Abstract: A system and method for maximizing bandwidth in an uplink for a 5G communication system is disclosed. Multiple end devices generate image streams. A gateway is coupled to the end devices. The gateway includes a gateway monitor agent collecting utilization rate data of the gateway and an image inspector collecting inspection data from the received image streams. An edge server is coupled to the gateway. The edge server includes an edge server monitor agent collecting utilization rate data of the edge server. An analytics manager is coupled to the gateway and the edge server. The analytics manager is configured to determine an allocation strategy based on the collected utilization rate data from the gateway and the edge server.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Quanta Cloud Technology Inc.
    Inventors: Yi-Neng Zeng, Keng-Cheng Liu, Wei-Ming Huang, Shih-Hsun Lai, Ji-Jeng Lin, Chia-Jui Lee, Liao Jin Xiang
  • Patent number: 11917344
    Abstract: Disclosed are an interactive information processing method, an electronic device and a storage medium. The method includes establishing a position correspondence between a display text generated based on a multimedia data stream and the multimedia data stream; and presenting the display text and the multimedia data stream corresponding to the display text based on the position correspondence.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 27, 2024
    Assignee: BEIJING ZITIAO NETWORK TECHNOLOGY CO., LTD.
    Inventors: Jingsheng Yang, Kojung Chen, Jinghui Liu, Mengyuan Xiong, Xiang Zheng, Cheng Qian, Xiao Han, Li Zhao