Abstract: A head mounted display device including a host, two brackets, and two rotating components is provided. The two brackets are respectively pivotally connected to opposite sides of the host. Each bracket includes a first segment and a second segment. The first segment is pivotally connected to the second segment, and the first segment is pivotally connected to the host. The two rotating components are respectively assembled to the first segment and the second segment of each bracket to control an angle between the first segment and the second segment.

Abstract: An antenna structure is configured to receive a set of feeding signals via a set of signal feeding nodes to resonate. The antenna structure includes a frame assembly and a radiation assembly. The frame assembly has four side walls. The four side walls form a resonance cavity. Two of the four side walls include two vias, and the two vias are electrically connected to the set of signal feeding nodes, and is configured to receive the set of feeding signals. The radiation assembly is correspondingly connected to the frame assembly. The two of the four side walls are adjacent to each other.

Abstract: A blockchain network includes a service sub-network, a consensus sub-network, and a routing layer configured to isolate the service sub-network from the consensus sub-network. A data processing method in the blockchain network includes: receiving a data processing request transmitted by a service node in the service sub-network; performing identity verification on the service node according to the data processing request; obtaining a running load of each consensus node in the consensus sub-network when the verification succeeds; determining, from the consensus sub-network according to the running load, a target consensus node configured to process the data processing request; and forwarding the data processing request to the target consensus node, and performing corresponding data processing on the data processing request by using the target consensus node.

Abstract: The present disclosure provides Low Temperature NOx-Absorber (LT-NA) catalyst compositions, catalyst articles, and an emission treatment system for treating an exhaust gas, each including the LT-NA catalyst compositions. Further provided are methods for reducing a NOx level in an exhaust gas stream using the LT-NA catalyst articles. In particular, the LT-NA catalyst compositions include a first zeolite, a first palladium component, and a plurality of platinum nanoparticles. The LT-NA catalyst compositions exhibit enhanced regeneration efficiency with respect to NOx adsorption capacity, even after hydrothermal aging.

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. A plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.

Abstract: The embodiments of the present disclosure provide a memory and a manufacturing method of a memory. The memory includes first fins and second fins disposed on a substrate, a dielectric layer covering tops of the first fins and side wall surfaces exposed by an isolating structure, and work function layers disposed on a surface of the dielectric layer. In a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the adjacent first fins are opposite are provided with a first thickness, and the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness. The first thickness is greater than the second thickness.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: Metal-comprising resist layers (for example, metal oxide resist layers), methods for forming the metal-comprising resist layers, and lithography methods that implement the metal-comprising resist layers are disclosed herein that can improve lithography resolution. An exemplary method includes forming a metal oxide resist layer over a workpiece by performing deposition processes to form metal oxide resist sublayers of the metal oxide resist layer over the workpiece and performing a densification process on at least one of the metal oxide resist sublayers. Each deposition process forms a respective one of the metal oxide resist sublayers. The densification process increases a density of the at least one of the metal oxide resist sublayers. Parameters of the deposition processes and/or parameters of the densification process can be tuned to achieve different density profiles, different density characteristics, and/or different absorption characteristics to optimize patterning of the metal oxide resist layer.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprise a substrate having a first region and a second region. A first gate overlies the first region. A second gate overlies the second region. A deep trench isolation (DTI) structure is in the substrate and laterally between the first region and the second region. A first floating diffusion node is in the first region. A second floating diffusion node is in the second region. An interlayer dielectric (ILD) structure is over the substrate. A dielectric structure is between the ILD structure and the substrate. The dielectric structure is laterally between the first and second floating diffusion nodes. The dielectric structure is laterally spaced from the first and second gates. The dielectric structure overlies the DTI structure. A width of the dielectric structure is greater than a width of the DTI structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device includes at least three metal plates that are spaced from one another. The MIM device further includes a plurality of capacitor insulator structures. Each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first superlattice structure and a second superlattice structure over the substrate, a gate stack that surrounds a channel region of each of the first superlattice structures and the second superlattice structure, and source/drain structures on opposite sides of the gate stack contacting sidewalls of the first superlattice structure and the second superlattice structure. The second superlattice structure is disposed over the first superlattice structure. Each of the first superlattice structures and the second superlattice structure includes vertically stacked alternating first nanosheets of a first semiconductor material and second nanosheets of a second semiconductor material that is different from the first semiconductor material.

Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.

Abstract: The driving circuit of the display includes a timing controller. The timing controller is coupled to a general purpose input/output (GPIO) pin of the touch driver. The timing controller receives an instruction signal via the GPIO pin of the touch driver. The timing controller starts a detection period according to a first edge switched from a first voltage level to a second voltage level of the instruction signal. The timing controller detects a number of pulse signals of the instruction signal, and determines a current operating status of the touch driver according to the number of pulse signals of the instruction signal during the detection period. The timing controller determines that the current operating status of the touch driver is one of touch operation type statuses according to the number of pulse signals of the instruction signal during the detection period being a default number.

Abstract: A memory includes a substrate; a plurality of bit lines on the substrate, which are parallel to each other and extend in a first direction; a plurality of active pillars on the bit lines, bottom ends of which are connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, which surround outer sidewalls of the active pillars, and expose top ends of the active pillars, the active pillars and the word lines jointly constitute vertical memory transistors of the memory; and a plurality of capacitors and a plurality of connecting pads, each of the capacitors is located on each of the active pillars, each of the connecting pads is located between the active pillar and the capacitor.

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

Abstract: A method for analyzing disaster prevention and mitigation effectiveness of an ecological seawall is provided, including: performing seawall ecologicalization on a target seawall; establishing three-dimensional space hydrodynamic force for the target ecological seawall; simulating wave climbing on a dike body and a wave overtopping on a dike top of the target ecological seawall to obtain a wave overtopping index; calculating wave-flow bottom shear stress of the target ecological seawall, establishing a sediment movement model, and calculating suspended load and bed load sediment transportation volumes; calculating the change index of coastal bed surface according to the suspended load and bed load sediment transportation volumes, and determining a development index of tidal flats in front of dike of the target ecological seawall according to the change index; and calculating the disaster prevention and mitigation effectiveness grade of the target ecological seawall according to the wave overtopping index and t

Abstract: Embodiments of this application relate to the field of communications technologies, and provide an information processing method and a device, to resolve a problem that activity information of an application on a terminal device cannot be obtained when the terminal device runs out of power. The method includes: A first terminal device obtains activity information of an application on the first terminal device when a battery level of the first terminal device is less than or equal to a first threshold. The first terminal device determines a second terminal device, where the second terminal device is a terminal device selected from an available device, the available device is an online device that uses a same user account as the first terminal device, and a battery level of the available device is greater than or equal to a second threshold. The first terminal device pushes the activity information of the application on the first terminal device to the second terminal device.

Abstract: The presently disclosed subject matter provides for methods and compositions for treating multiple myeloma. It relates to chimeric antigen receptors (CARs) that specifically target a G-protein coupled receptor (e.g., a G-protein coupled receptor family C group 5 member D (GPRC5D)), and immunoresponsive cells comprising such CARs. The presently disclosed CARs targeting a G-protein coupled receptor (e.g., GPRC5D) have enhanced immune-activating properties, including anti-tumor activity.