Abstract: A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.

Abstract: A substrate voltage generating circuit for use in a semiconductor memory device is provided. The semiconductor memory device includes a charge pump for generating a substrate bias voltage in response to a clock signal; a first inverter type detector for detecting whether the substrate bias voltage reaches a target voltage; a second differential amplifier type detector for detecting whether the substrate bias voltage reaches the target voltage; and a driver for generating the clock signal in response to an output of one of the first and second detectors.

Abstract: Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Abstract: An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active. The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.

Abstract: Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.

Abstract: Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.

Abstract: In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in response to a row active command, and generates the active kicker drive signal having a second pulse duration in response to a refresh command. An active kicker circuit is responsive to the active kicker drive signal to generate the boosted voltage. The second pulse duration may be greater than the first pulse duration, which makes it possible to improve the pumping efficiency of the boosted voltage in a refresh operation.

Abstract: An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.

Abstract: Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in syn

Abstract: Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.

Abstract: Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Abstract: A redundancy repair circuit and method therefor for use with a semiconductor memory device are provided. The redundancy repair circuit comprises: a memory circuit having a plurality of address lines and a plurality of redundancy address lines in a memory cell; a repair redundancy control circuit for repairing a defective address line using a redundancy address line of the plurality of redundancy address lines, and for encoding and outputting fuse repair information corresponding to redundancy address information, wherein addresses corresponding to defective memory cells are pre-programmed; and a redundancy line driver for receiving the fuse repair information from the repair redundancy control circuit, for decoding the fuse repair information and for activating a redundancy line corresponding to the decoded fuse repair information, wherein the repair redundancy control circuit is separate from the redundancy line driver.

Abstract: A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Abstract: Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Abstract: Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.

Abstract: Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the D