Patents by Inventor Chieh Wu

Chieh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11929986
    Abstract: Methods, systems, and computer programs are presented for enabling automated secure data sharing from a private cloud region to a public cloud region and vice versa. A cloud data platform confirms a relationship establishment procedure between a provider and a consumer is recorded with a cloud data platform, the provider being associated with a private cloud deployment and the consumer being associated with a public cloud deployment in a public region. The cloud data platform enables disabling of a firewall policy that is preventing data traffic between the private cloud deployment and the public cloud deployment and enables data sharing between the private cloud deployment and the public cloud deployment. The cloud data platform enables data sharing in a database of the cloud data platform.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: March 12, 2024
    Assignee: Snowflake Inc.
    Inventors: Khondokar Sami Igram, Laxman Mamidi, Sanjay Srivastava, Chieh-Sheng Wang, Di Wu
  • Patent number: 11927799
    Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 12, 2024
    Inventors: Po-Kuan Shen, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu, Chao-Chieh Hsu
  • Publication number: 20240079075
    Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Publication number: 20240075082
    Abstract: Provided is a composition including a lactic acid bacterium and a carrier thereof for prophylaxis or treatment of an allergy. The lactic acid bacterium is Lactobacillus paragasseri, such as Lactobacillus paragasseri BBM171 deposited under DSMZ Accession No. DSM 34311. Also provided is a method for preventing or treating an allergy in a subject that includes administering an effective amount of the composition of Lactobacillus paragasseri to the subject.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 7, 2024
    Inventors: Ying-Chieh Tsai, Yu-Hsuan Wei, Chih-Chieh Hsu, Chien-Chen Wu
  • Publication number: 20240075346
    Abstract: An exercise monitoring method, an exercise monitoring device, and a computer-readable storage medium are provided. The method includes the following: obtaining an exercise course input by a user; detecting a reference respiratory pattern of the user performing the exercise course through a wearable device within a reference time interval; detecting a first respiratory pattern of the user performing the exercise course through the wearable device within a first time interval; and providing a first exercise adjustment suggestion based on a first comparison result between the first respiratory pattern and the reference respiratory pattern.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Applicant: BOMDIC INC.
    Inventors: Yao Shiao, Shih-Chieh Wu
  • Publication number: 20240079080
    Abstract: A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Patent number: 11923251
    Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hsiu Perng, Kai-Chieh Yang, Zhi-Chang Lin, Teng-Chun Tsai, Wei-Hao Wu
  • Patent number: 11923252
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
  • Patent number: 11923386
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240071538
    Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
  • Patent number: 11917144
    Abstract: Various schemes for realizing efficient in-loop filtering are described, manifested in low latency and reduced hardware cost for an in-loop filter comprising at least two filtering stages. An apparatus receives pixel data of a current block of a picture and one or more neighboring blocks thereof, based on which the apparatus performs a filtering operation and generates a filtered block that includes completely filtered sub-blocks and partially filtered sub-blocks. The apparatus further outputs an output block that includes the completely filtered sub-blocks as well as a respective portion of each of the partially filtered sub-blocks, wherein the respective portion is adjacent to one of the completely filtered sub-blocks.
    Type: Grant
    Filed: June 19, 2022
    Date of Patent: February 27, 2024
    Assignee: MediaTek Inc.
    Inventors: Yueh-Lin Wu, Min-Hao Chiu, Yen-Chieh Huang
  • Patent number: 11915733
    Abstract: A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang
  • Publication number: 20240063075
    Abstract: A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pavithra Sriram, Kuo-Lung Pan, Po-Yuan Teng, Cheng-Chieh Wu, Mao-Yen Chang, Yu-Chia Lai, Shu-Rong Chun, Hao-Yi Tsai
  • Patent number: 11904399
    Abstract: An online prediction method of tool-electrode consumption adapted for an electrical discharge machining (EDM) apparatus includes an experimental design; extracting electrode consumption variables from machining parameters of the electrical discharge machining (EDM) apparatus; and obtaining a correlation between the machining parameters and the electrode consumption variables through a correlation analysis to obtain a prediction model capable of predicting an effective contact area of a tool-electrode and a workpiece. In addition, a prediction method of machining accuracy is provided.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: February 20, 2024
    Assignee: Metal Industries Research & Development Centre
    Inventors: Chia-Ming Jan, Wen-Chieh Wu
  • Patent number: 11904443
    Abstract: A clamping device includes a fixing clamp and a positioning clamp for clamping two plate pieces. The positioning clamp includes a main body having a first abutment surface and a second abutment surface separated by an abutment angle and suitable for respectively abutting against first plate surfaces of the plate pieces. A reversing mechanism includes a reversing member rotatably disposed in the main body and having a limiting portion. The reversing member is rotatable relative to the main body between a first side and a second side, in which the limiting portion is aligned with the first abutment surface and the second abutment surface, respectively, and is suitable for abutting against the end surfaces of the plate pieces.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: February 20, 2024
    Inventor: Ming-Chieh Wu
  • Patent number: 11892562
    Abstract: A performing device of an impulse-like gesture recognition system executes an impulse-like gesture recognition method. A performing procedure of the impulse-like gesture recognition method includes steps of: receiving a sensing signal from a sensing unit; determining a prediction with at least one impulse-like label according to the sensing frames by a deep learning-based model; and classifying at least one gesture event according to the prediction. The gesture event is classified to determine the motion of the user. Since the at least one impulse-like label is used to label at least one detection score of the deep learning-based model, the detection score is non-decreasing, reaction time of the at least one gesture event for an incoming gesture is fast, rapid consecutive gestures are easily decomposed, and an expensive post-processing is not needed.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: February 6, 2024
    Assignee: KaiKuTek Inc.
    Inventors: Mike Chun-Hung Wang, Chun-Hsuan Kuo, Wen-jyi Hwang, Guan-Sian Wu, Chieh Wu, Wen-Yen Chou, Yu-Feng Wu, Fang Li, Wen-Yen Chang
  • Publication number: 20240019486
    Abstract: A method includes forming a reconstructed wafer, which includes placing a plurality of package components over a carrier, forming an interconnect structure over and electrically interconnecting the plurality of package components, forming top electrical connectors over and electrically connecting to the interconnect structure, and forming alignment marks at a same level as the top electrical connectors. Probe pads in the top electrical connectors are probed, and the probing is performed using the alignment marks for aligning to the probe pads. An additional package component is bonded to the reconstructed wafer through solder regions. The solder regions are physically joined to the top electrical connectors.
    Type: Application
    Filed: January 9, 2023
    Publication date: January 18, 2024
    Inventors: Cheng-Chieh Wu, Kuo-Lung Pan, Shu-Rong Chun, Hao-Yi Tsai, Po-Yuan Teng, Mao-Yen Chang, Cheng Yu Liu, Chia-Wen Lin
  • Publication number: 20240008217
    Abstract: A thermal dissipation device for a handheld electronic device is provided. The thermal dissipation device includes a thermoelectric cooling chip, a temperature sensor, a humidity sensor, and a processing unit. The thermoelectric cooling chip has a cold surface and a hot surface. The cold surface is attached on a heating surface of the handheld electronic device by means of a heat conduction structure, and has a cold surface temperature. The temperature sensor and the humidity sensor are disposed in an area adjacent to the thermoelectric cooling chip for generating an environmental temperature and an environmental humidity respectively. The processing unit is configured to calculate a dew point temperature based on the environmental temperature and the environmental humidity; and determine whether to stop the thermoelectric cooling chip or not based on the cold surface temperature, the dew point temperature, and a heating surface temperature of the handheld electronic device.
    Type: Application
    Filed: January 20, 2023
    Publication date: January 4, 2024
    Inventors: Jyun-Miao HONG, Jhih-Wei RAO, Zih-Siang HUANG, Chieh LI, Chen-Yu HSU, Chih-Hsien YANG, Hung-Chieh WU, Liang-Jen LIN
  • Publication number: 20240008227
    Abstract: A heat dissipation holder applied to a handheld electronic device is provided. The heat dissipation holder includes a base, a cover, a heat dissipation module, and an air guiding structure. The base includes a first side and a second side that are opposite to each other and a front surface and a rear surface that are opposite to each other. The first side includes a first opening. The cover is combined onto the front surface to form an accommodating space with the base. The cover includes an air inlet region. The heat dissipation module is disposed in the accommodating space. The air guiding structure is disposed on the cover and extends to the first opening. The first opening, the air inlet region, and the air guiding structure form an airflow channel between the heat dissipation module and the cover.
    Type: Application
    Filed: January 13, 2023
    Publication date: January 4, 2024
    Inventors: Jhih-Wei RAO, Zih-Siang HUANG, Hung-Chieh WU, Liang-Jen LIN