Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

Abstract: A computer-implement operating method includes periodically generating sensing data by determining a triggered area of each of the sensors of a surface on which each of the sensors disposed; grouping effective sensors among the sensors into a plurality of sensor groups respectively corresponding to the fingers; obtaining a bending angle of one finger among the fingers according to the sensing values of the sensing data of all effective sensors in one sensor group corresponding to the said one finger among the sensor groups; and bending one virtual finger corresponding to the said one finger among virtual fingers of a virtual hand rendered in a virtual space corresponding to the electronic system according to the obtained bending angle of the said one finger, so as to render the virtual hand having a gesture matching to a gesture of the hand sensed by the controller.

Abstract: A head mounted displaying system and an image generating method thereof are provided. The head mounted displaying system includes a displaying device, a movement sensor, a frame, an image generating system and a physiological information sensor. The movement sensor senses a movement of an object or senses a movement of the displaying device. The frame is configured to fix the displaying device. The image generating system is coupled to the displaying device. The image generating system displays an image through the displaying device. The image includes a first part. The first part is irrelative to a sensing result of the movement sensor. The physiological information sensor is disposed at the frame and coupled to the image generating system. The image generating system adjusts the first part of the image displayed by the displaying device according to physiological information sensed by the physiological information sensor.

Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.

Abstract: A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.

Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.

Abstract: A memory device including a plurality of memory units; at least one geometric mean operator coupled to at least two of the plurality of memory units; and a memory state reader coupled to the at least one geometric mean operator to read a memory state of the plurality of memory units.

Abstract: A finger-gesture detection device adapted for a control handle includes a grip portion. The finger-gesture detection device includes a first wearing portion, a plurality of second wearing portions, and a plurality of first sensors. The first wearing portion is adapted to detachably surround the grip portion of the control handle. When the grip portion connects the first wearing portion, the grip portion is positioned on one side of the first wearing portion. The second wearing portions are each independently connected to the first wearing portion. When a force is applied to one of the second wearing portions, the corresponding second wearing portion moves toward the grip portion. The first sensors are respectively disposed on the second wearing portions for detecting positions or movements of the second wearing portions relative to the grip portion. A control assembly and a correction method are also proposed.

Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.

Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.

Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.

Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.

Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.

Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.

Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.

Abstract: A high-reliability resistive random access memory (RRAM). A memory cell of a memory cell array is controlled via a word line, a bit line and a source line. The control unit of the RRAM has a word line decoder, a bit line decoder, and a source line decoder and switch circuit. The word line decoder, the bit line decoder and the source line decoder respectively control the voltage applied to the word line, the voltage applied to the bit line, and the voltage applied to the source line. The switch circuit is switched between a first state and a second state to operate the bit line decoder to apply a voltage to the bit line to read the memory cell and to operate the source line decoder to apply a voltage to the source line to read the memory cell alternately.

Abstract: A memory driving device and a method thereof applied for a RRAM array are provided. The memory driving device includes a voltage generator, a current detector, and a controller. The voltage generator generates a write voltage. An RRAM cell of the RRAM array is selected according to a selection signal for receiving the program voltage to generate a program current. The current detector detects the program current. The controller executes a driving procedure which includes: obtaining a voltage distribution for the program voltage; determining the initial voltage and the maximum voltage of the program voltage according to the voltage distribution; gradually increasing the program voltage from the initial voltage to the maximum voltage; determining whether the program current exceeds the reference current; and selecting another RRAM cell when the write current exceeds the reference current.

Abstract: The present invention provides an operation method for RRAM. The operation method includes providing a reset voltage pulse to a RRAM, providing a dummy voltage pulse to the RRAM, and providing a verification voltage pulse to the RRAM. The reset current of the RRAM is read when the verification voltage pulse is provided. The voltage level of the verification voltage pulse is higher than the voltage level of the read voltage pulse for reading the RRAM.

Abstract: A memory driving device and a method thereof applied for a RRAM array are provided. The memory driving device includes a voltage generator, a current detector, and a controller. The voltage generator generates a write voltage. An RRAM cell of the RRAM array is selected according to a selection signal for receiving the program voltage to generate a program current. The current detector detects the program current. The controller executes a driving procedure which includes: obtaining a voltage distribution for the program voltage; determining the initial voltage and the maximum voltage of the program voltage according to the voltage distribution; gradually increasing the program voltage from the initial voltage to the maximum voltage; determining whether the program current exceeds the reference current; and selecting another RRAM cell when the write current exceeds the reference current.

Abstract: The present invention provides an operation method for RRAM. The operation method includes providing a reset voltage pulse to a RRAM, providing a dummy voltage pulse to the RRAM, and providing a verification voltage pulse to the RRAM. The reset current of the RRAM is read when the verification voltage pulse is provided. The voltage level of the verification voltage pulse is higher than the voltage level of the read voltage pulse for reading the RRAM.