Patents by Inventor Chien-Min Wu

Chien-Min Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070251272
    Abstract: A rectangular monobloc optical lens and a manufacturing method thereof are disclosed. A monobloc optical lens includes a rectangular surround and a central mirror-surface area. The rectangular surround is mounted inside a clipping part of a lens holder. The central mirror-surface area consists of a convex aspherical surface and a concave aspherical surface while the convex aspherical surface faces an image side and the concave aspherical surface faces an object side. The manufacturing method includes the steps of: cutting a sheet made from glass material into a plurality of rectangular sheet units; then setting the rectangular sheet unit into a mold for lens for hot pressing. Thereby, the manufacturing process is simplified and the cost is reduced. Moreover, the lens has high resolution and the volume of the lens is effectively reduced so as to increase the applications of the lens.
    Type: Application
    Filed: July 13, 2007
    Publication date: November 1, 2007
    Inventors: San-Woei Shyu, Chien-Min Wu
  • Publication number: 20070241274
    Abstract: An apparatus-testing mask and a method for calibrating essential parameters of exposure apparatuses on the optics principle base are provided. The mask includes a light-transparent substrate and calibration patterns disposed on the light-transparent substrate. Wherein, each of the calibration patterns includes a recognition pattern having symmetricity, a comparison pattern disposed around the recognition pattern and two pairs of calibration reticles disposed around the comparison pattern and extending along four directions (for example, 0°, 45°, 90° and 135°), respectively. By using the mask to calibrate the exposure apparatuses, the uptime of the exposure apparatuses is enhanced, the masks used for calibration are unified and some essential parameters of an exposure apparatus, such as focal length, skew degree and phase error are able to be calibrated using an auto-feedback system.
    Type: Application
    Filed: September 27, 2005
    Publication date: October 18, 2007
    Inventors: Ching-Hsiang Chang, Chien-Min Wu
  • Publication number: 20070171535
    Abstract: A rectangular monobloc optical lens and a manufacturing method thereof are disclosed. A monobloc optical lens includes a rectangular surround and a central mirror-surface area. The rectangular surround is mounted inside a clipping part of a lens holder. The central mirror-surface area consists of a convex aspherical surface and a concave aspherical surface while the convex aspherical surface faces an image side and the concave aspherical surface faces an object side. The manufacturing method includes the steps of: cutting a sheet made from glass material into a plurality of rectangular sheet units; then setting the rectangular sheet unit into a mold for lens for hot pressing. Thereby, the manufacturing process is simplified and the cost is reduced. Moreover, the lens has high resolution and the volume of the lens is effectively reduced so as to increase the applications of the lens.
    Type: Application
    Filed: April 14, 2006
    Publication date: July 26, 2007
    Inventors: San-Woei Shyu, Chien-Min Wu
  • Patent number: 7184336
    Abstract: A method for evaluating threshold voltage distribution of memory cells. The method comprises connecting all sources and drains of memory cells in a memory array to a fixed voltage; measuring charge pumping current characteristic of a single memory cell versus a first gate voltage and second gate voltage respectively. The total charge pumping current characteristic of a memory array is then measured versus a first gate voltage and second gate voltage respectively. The charge pumping current characteristics of the single memory cell is compared to that of the memory array to obtain a range of threshold voltage distribution.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: February 27, 2007
    Assignee: Winbond Electronics Corp.
    Inventors: Lu-Ping Chiang, Chien-Min Wu, Po-An Chen
  • Publication number: 20060039212
    Abstract: A method for evaluating threshold voltage distribution of memory cells. The method comprises connecting all sources and drains of memory cells in a memory array to a fixed voltage; measuring charge pumping current characteristic of a single memory cell versus a first gate voltage and second gate voltage respectively. The total charge pumping current characteristic of a memory array is then measured versus a first gate voltage and second gate voltage respectively. The charge pumping current characteristics of the single memory cell is compared to that of the memory array to obtain a range of threshold voltage distribution.
    Type: Application
    Filed: April 13, 2005
    Publication date: February 23, 2006
    Inventors: Lu-Ping chiang, Chien-Min Wu, Po-An Chen
  • Patent number: 6862219
    Abstract: A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as zero volt, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: March 1, 2005
    Assignee: Winbond Electronics Corp.
    Inventors: Shih-Hsien Yang, Chien-Min Wu, James Juen Hsu, Chi-Moon Huang
  • Publication number: 20040184320
    Abstract: A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as zero volt, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.
    Type: Application
    Filed: March 19, 2003
    Publication date: September 23, 2004
    Inventors: Shih-Hsien Yang, Chien-Min Wu, James Juwn Hsu, Chi-Moon Huang