Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: A button mechanism is provided, including a button element, a magnet connected to the button, a hollow tube, a first coil, and a second coil. The first and second coils are disposed on the tube. When the first coil generates a first magnetic field, the magnet is magnetically attracted by the first coil, and the button element is positioned in the first position. When the second coil generates a second magnetic field, the magnet is attracted by the second coil, and the button element is positioned in the second position.

Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.

Abstract: A casing structure with functionality of effective thermal management is disclosed, which consists of a casing member, a low thermal conductivity medium, a second heat spreader, and a first heat spreader. When a user operates the electronic device, heat generated from CPU and/or GPU is transferred to the second heat spreader via the first heat spreader, and then is two-dimensionally spread in the second heat spreader. Consequently, the heat is dissipated away from the casing member to air due to the outstanding thermal radiation ability of the casing member. The low thermal conductivity medium is adopted for controlling a heat transfer of heat transferring paths from the heat source and ends to the casing member. By applying the casing structure in an electronic device by a form of a top casing and/or a back casing, an outer surface temperature of the casing member can be well controlled.

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

Abstract: A casing structure with functionality of effective thermal management is disclosed, which consists of a casing member, a low thermal conductivity medium, a second heat spreader, and a first heat spreader. When a user operates the electronic device, heat generated from CPU and/or GPU is transferred to the second heat spreader via the first heat spreader, and then is two-dimensionally spread in the second heat spreader. Consequently, the heat is dissipated away from the casing member to air due to the outstanding thermal radiation ability of the casing member. The low thermal conductivity medium is adopted for controlling a heat transfer of heat transferring paths from the heat source and ends to the casing member. By applying the casing structure in an electronic device by a form of a top casing and/or a back casing, an outer surface temperature of the casing member can be well controlled.

Abstract: The present invention provides a circuitry within a router or a switch, wherein the circuitry comprises a priority decision circuitry and a per-stream filtering and policing circuitry. The priority decision circuitry is configured to determine a priority of a frame received from a port of the router or the switch. The per-stream filtering and policing circuitry is configured to classify the frame into a first-type frame, a second-type frame or a third-type frame, wherein if the frame is determined as the first-type frame, the per-stream filtering and policing circuitry forwards the frame; if the frame is determined as the third-type frame, the per-stream filtering and policing circuitry discards the frame; and if the frame is determined as the second-type frame, the per-stream filtering and policing circuitry changes the priority of the frame, and the per-stream filtering and policing circuitry forwards the frame with the changed priority.

Abstract: The present disclosure pertains to an electromagnetic-wave shielding film and a preparation method thereof. The electromagnetic-wave shielding film includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer has two opposite surfaces. The insulating layer is disposed on one of the surfaces of the first metal layer. The second metal layer is disposed on the other surface of the first metal layer and contains nano metal particles and an binder. The electromagnetic-wave shielding film can be used in a printed circuit board, and shows a satisfactory electromagnetic wave shielding effect.

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

Abstract: The present disclosure pertains to an electromagnetic-wave shielding film and a preparation method thereof. The electromagnetic-wave shielding film includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer has two opposite surfaces. The insulating layer is disposed on one of the surfaces of the first metal layer. The second metal layer is disposed on the other surface of the first metal layer and contains nano metal particles and an binder. The electromagnetic-wave shielding film can be used in a printed circuit board, and shows a satisfactory electromagnetic wave shielding effect.

Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.