Patents by Inventor Chih-Ching Chen

Chih-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220183186
    Abstract: A casing structure with functionality of effective thermal management is disclosed, which consists of a casing member, a low thermal conductivity medium, a second heat spreader, and a first heat spreader. When a user operates the electronic device, heat generated from CPU and/or GPU is transferred to the second heat spreader via the first heat spreader, and then is two-dimensionally spread in the second heat spreader. Consequently, the heat is dissipated away from the casing member to air due to the outstanding thermal radiation ability of the casing member. The low thermal conductivity medium is adopted for controlling a heat transfer of heat transferring paths from the heat source and ends to the casing member. By applying the casing structure in an electronic device by a form of a top casing and/or a back casing, an outer surface temperature of the casing member can be well controlled.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 9, 2022
    Applicant: AMLI MATERIALS TECHNOLOGY CO., LTD.
    Inventors: JIAN-JIA HUANG, CHUN-KAI LIN, CHIH-CHING CHEN
  • Publication number: 20210344605
    Abstract: The present invention provides a circuitry within a router or a switch, wherein the circuitry comprises a priority decision circuitry and a per-stream filtering and policing circuitry. The priority decision circuitry is configured to determine a priority of a frame received from a port of the router or the switch. The per-stream filtering and policing circuitry is configured to classify the frame into a first-type frame, a second-type frame or a third-type frame, wherein if the frame is determined as the first-type frame, the per-stream filtering and policing circuitry forwards the frame; if the frame is determined as the third-type frame, the per-stream filtering and policing circuitry discards the frame; and if the frame is determined as the second-type frame, the per-stream filtering and policing circuitry changes the priority of the frame, and the per-stream filtering and policing circuitry forwards the frame with the changed priority.
    Type: Application
    Filed: December 10, 2020
    Publication date: November 4, 2021
    Inventors: Chung-Keng Hung, Yung-Kun Lin, Chih-Ching Chen, Ta-Chin Tseng
  • Patent number: 11129313
    Abstract: The present disclosure pertains to an electromagnetic-wave shielding film and a preparation method thereof. The electromagnetic-wave shielding film includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer has two opposite surfaces. The insulating layer is disposed on one of the surfaces of the first metal layer. The second metal layer is disposed on the other surface of the first metal layer and contains nano metal particles and an binder. The electromagnetic-wave shielding film can be used in a printed circuit board, and shows a satisfactory electromagnetic wave shielding effect.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 21, 2021
    Assignee: ETERNAL MATERIALS CO., LTD.
    Inventors: Shu-Hung Liu, Chih-Ching Chen, Chin-Yi Liao
  • Publication number: 20200365572
    Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 19, 2020
    Inventors: Yao-Chun Su, Chih-Ching Chen, I-Hsuan Peng, Yi-Jou Lin
  • Publication number: 20200128704
    Abstract: The present disclosure pertains to an electromagnetic-wave shielding film and a preparation method thereof. The electromagnetic-wave shielding film includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer has two opposite surfaces. The insulating layer is disposed on one of the surfaces of the first metal layer. The second metal layer is disposed on the other surface of the first metal layer and contains nano metal particles and an binder. The electromagnetic-wave shielding film can be used in a printed circuit board, and shows a satisfactory electromagnetic wave shielding effect.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 23, 2020
    Applicant: ETERNAL MATERIALS CO., LTD.
    Inventors: Shu-Hung Liu, Chih-Ching Chen, Chin-Yi Liao
  • Patent number: 9792722
    Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: October 17, 2017
    Assignee: MediaTek Inc.
    Inventors: Ming-Hao Liao, Chih-Ching Chen, Hung-Wei Wu
  • Patent number: 9503292
    Abstract: A method for calculating a feed forward equalizer coefficient of a feed forward equalizer in a minimum mean square error decision feedback equalizer (MMSE-DFE) based on a fast transversal recursive least squares (FT-RLS) algorithm is provided. The length of the feed-forward equalizer is LF, which is a positive integer. The method includes an outer iteration having an LF number of iterations. The outer iteration includes an inner iteration having an n number of iterations, where n is an integer between 0 and (LF?2).
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 22, 2016
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Ching-Wen Ma, Chih-Cheng Kuo, Tai-Lai Tung, Chih-Ching Chen
  • Publication number: 20160180579
    Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Ming-Hao Liao, Chih-Ching Chen, Hung-Wei Wu
  • Publication number: 20160180539
    Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Ming-Hao Liao, Chih-Ching Chen, Shih-Chin Lin, Hung-Wei Wu
  • Patent number: 9361697
    Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 7, 2016
    Assignee: MEDIATEK INC.
    Inventors: Ming-Hao Liao, Chih-Ching Chen, Shih-Chin Lin, Hung-Wei Wu
  • Patent number: 9228133
    Abstract: A method for refining oil includes contacting an oil with hydrogen to perform a hydrodeoxygenation reaction using iron oxide as a catalyst. The iron oxide comprises ferrous oxide (FeO), ferrum dioxide (FeO2), ferric oxide (Fe2O3), ferroferric oxide (Fe3O4), or combinations thereof.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 5, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chiung-Fang Liu, Ching-I Juch, Chih-Hao Chen, Chih-Ching Chen, Ju-Shiou Chen, Ying-Hsi Chang, Hou-Peng Wan, Hom-Ti Lee
  • Patent number: 9152553
    Abstract: The present disclosure includes systems and techniques relating to controlling memory devices with a generic command descriptor. In some implementations, an apparatus, systems, or methods can include a memory controller including an interface configured to connect with a NAND memory device and circuitry configured to receive a descriptor of a command sequence including multiple segments for managing the NAND memory device. The descriptor can include option information corresponding to each segment of the command sequence. The circuitry can also be configured to generate the command sequence for managing the NAND memory device based, at least in part, on the option information of the descriptor.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: October 6, 2015
    Assignee: Marvell International Ltd.
    Inventors: Hyunsuk Shin, Chi Kong Lee, Chih-Ching Chen
  • Patent number: 9147470
    Abstract: Apparatus for programming a non-volatile memory, the apparatus having corresponding methods and tangible computer-readable media, comprise: a command memory configured to hold a plurality of command templates, wherein each of the command templates specifies a sequence of pad signals; a state machine configured to i) receive descriptors, wherein each of the descriptors includes a pointer to a respective one of the command templates in the command memory, and ii) generate the sequence of pad signals based on the command template indicated by the respective pointer; and a non-volatile memory interface configured to provide, to pads of the non-volatile memory, the sequence of pad signals generated by the state machine.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: September 29, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Chih-Ching Chen, Hyunsuk Shin, Chi Kong Lee, Xueting Yu
  • Patent number: 9146824
    Abstract: The present disclosure includes systems and techniques relating to management of bit line errors based on a stored set of data. In some implementations, a system can include a device including non-volatile solid state memory and a memory controller. The memory controller can be configured to identify, from the solid state memory of the device, one or more bit line errors for the device upon power up of the system, construct a set of data corresponding to the one or more bit line errors for the device, store the set of data, at least in part, in the device, and, upon a subsequent power up of the system, identify the one or more bit line errors for the device from the stored set of data.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 29, 2015
    Assignee: Marvell International Ltd.
    Inventors: Chih-Ching Chen, Hyunsuk Shin, Chi Kong Lee, Siu-Hung Frederick Au, Jungil Park, Fei Sun
  • Patent number: 8964498
    Abstract: In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: February 24, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Hyunsuk Shin, Jungil Park, Chi Kong Lee, Chih-Ching Chen
  • Patent number: 8935545
    Abstract: A power generator adaptive to a computer apparatus is provided. The power generator includes a logic operating unit, a power converting module, and a power management module. The logic operating unit receives a power pulse signal generated by a power button when the power button is pressed. The logic operating unit generates a power enabling signal according to the power pulse signal. The power converting module receives the power enabling signal and generates an internal voltage by converting an external voltage according to the power enabling signal. The power management module receives the internal voltage and the power pulse signal, and latches a generating state of the internal voltage according to the power pulse signal to generate a power stable signal. The power management module further provides the power stable signal to the logic operating unit to maintain a generating state of the power enabling signal.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: January 13, 2015
    Assignee: ASUSTeK Computer Inc.
    Inventors: Shang-Yu Hung, Chih-Ching Chen
  • Publication number: 20140352763
    Abstract: A frame of a photovoltaic panel includes at least one L-shaped corner joint at least one first frame body and at least one second frame body. The L-shaped corner joint includes a support, a first joint arm and a second joint arm respectively disposed on different surfaces of the support, wherein the first joint arm and the second joint arm respectively have at least one first riveting hole and at least one second riveting hole. The first frame body has a first engaging groove therebetween. The first joint arm is inserted in the first engaging groove. Part of the first inner frame plate is caved in the first riveting hole. The second frame body has a second engaging groove. The second joint arm is inserted in the second engaging groove. Part of the second inner frame plate is caved in the second riveting hole.
    Type: Application
    Filed: July 31, 2013
    Publication date: December 4, 2014
    Applicant: Gintech Energy Corporation
    Inventors: Yu-Min CHEN, Jiunn-Chenn LU, Hsu-Ting CHANG, Chih-Ching CHEN
  • Patent number: 8648218
    Abstract: In an embodiment of the disclosure, a method for preparing a phenolic compound is provided. The method includes providing a lignin depolymerization product, and hydrogenating the lignin depolymerization product under iron oxide and hydrogen gas to prepare a phenolic compound. The prepared phenolic compound is a crude phenolic composition including phenol, methylphenol, dimethylphenol or a combination thereof.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 11, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chiung-Fang Liu, Chih-Ching Chen, Chih-Hao Chen, Pei-Jung Yu, Ying-Hsi Chang, Hou-Peng Wan, Hom-Ti Lee
  • Patent number: 8467280
    Abstract: A controller of an optical storage apparatus for generating a plurality of control signals is provided. The controller includes a code generator implemented for determining a plurality of control codes according to an input data associated with data recording, and generating the control signals to deliver the control codes. Each of the control codes represents one power level. Besides, regarding each of the control signals, a minimum transmission pulse length thereof corresponds to more than one power symbol period.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 18, 2013
    Assignee: Mediatek Inc.
    Inventors: Gwo-Huei Wu, Pi-Hai Liu, Chih-Ching Chen
  • Patent number: 8451971
    Abstract: A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: May 28, 2013
    Assignee: Mediatek Inc.
    Inventors: Kuan-Hua Chao, Shiue-Shin Liu, Jeng-Horng Tsai, Chih-Ching Chen, Chuan Liu, Tse-Hsiang Hsu