Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

Abstract: A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.

Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.

Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

Abstract: A manufacturing method of a package includes at least the following steps. A carrier is provided. An inductor is formed over the carrier. The inductor includes a first portion, a second portion, and a third portion. The first portion is parallel to the third portion, and the second portion connects the first portion and the third portion. A die is placed over the carrier. The die is surrounded by the inductor. An encapsulant is formed between the first portion and the third portion of the inductor. The encapsulant laterally encapsulates the die and the second portion of the inductor.

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: A package includes a first redistribution structure, a die, an encapsulant, a second redistribution structure, and an inductor. The die is disposed on the first redistribution structure. The encapsulant laterally encapsulates the die. The second redistribution structure is over the die and the encapsulant. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure. The second portion is embedded in the encapsulant and is connected to the first and third portions of the inductor. The third portion is embedded in the second redistribution structure.

Abstract: An apparatus includes a semiconductor component and a cooling structure. The cooling structure is over a back side of the semiconductor component. The cooling structure includes a housing, a liquid delivery device and a gas exhaust device. The housing includes a cooling space adjacent to the semiconductor component. The liquid delivery device is connected to an inlet of the housing and is configured to deliver a liquid coolant into the cooling space from the inlet. The gas exhaust device is connected to an outlet of the housing and is configured to lower a pressure in the housing.

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.

Abstract: A method of manufacturing a semiconductor device includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate of an antenna structure and a first dielectric layer laterally surrounding the first conductive plate; etching the first dielectric layer to form a recess exposing the first conductive plate; filling the recess with a second dielectric material to form an insulating film; and forming a second redistribution layer including a second conductive plate of the antenna structure over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, wherein one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave. The insulating film has a thickness associated with a main resonance frequency of the antenna structure.