Patents by Inventor Chih-Hung Wu

Chih-Hung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11888845
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 30, 2024
    Assignee: KINGSTON DIGITAL, INC.
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Patent number: 11736108
    Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: August 22, 2023
    Assignee: Faraday Technology Corp.
    Inventors: Ko-Ching Chao, Chih-Hung Wu, Po-Wen Hsiao, Zhou-Lun Liou
  • Publication number: 20230231560
    Abstract: A method for performing divided-clock phase synchronization in a multi-divided-clock system, an associated synchronization control circuit, an associated synchronization control sub-circuit and an associated electronic device are provided. The method may include: performing frequency division operations according to a source clock to generate a first divided clock and a second divided clock; performing phase relationship detection on the first divided clock according to the second divided clock to generate a phase relationship detection result signal; performing a logic operation on a first phase selection result output signal and the phase relationship detection result signal to generate a second phase selection result output signal; and outputting one of the second divided clock and an inverted signal of the second divided clock according to the second phase selection result output signal, for further use in a physical layer circuit.
    Type: Application
    Filed: October 27, 2022
    Publication date: July 20, 2023
    Applicant: Faraday Technology Corp.
    Inventors: Ko-Ching Chao, Chih-Hung Wu, Po-Wen Hsiao, Zhou-Lun Liou
  • Patent number: 11606091
    Abstract: An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: March 14, 2023
    Assignee: FARADAY TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Wu, Yu-Chieh Ma
  • Patent number: 11584670
    Abstract: A bio-trickling filter box device capable of purifying organic wastewater and generating electricity is provided, which includes battery component(s) and a bio-trickling filter box component. The battery component(s) is provided in the bio-trickling filter box. The other end of each of trickling filter tube(s) is connected with a water tank. A water pump operates to make water flow through the trickling filter tube(s), pass through leakage holes and trickling holes, and drip into the battery component(s) in a water-drop manner, so as to supply an electric apparatus component with power. The bio-trickling filter box component(s) and the battery component(s) are combined, and the long-term impingement of water droplets on the battery component(s) can accumulate electric charge and generate the electricity. so as to provide power required by the electric apparatus component, which forms a biological treatment system that generates the power while treating the wastewater.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 21, 2023
    Assignee: Sanming University
    Inventors: Chih-Hung Wu, Xiang Wang, Jer-Yuan Shih, Ching-Hua Liao, Hongduo Li, Bin Ouyang, Zhigang Wu, Lingwei Yang, Tingliang Liu
  • Publication number: 20220182055
    Abstract: An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.
    Type: Application
    Filed: August 11, 2021
    Publication date: June 9, 2022
    Inventors: Chih-Hung WU, Yu-Chieh MA
  • Publication number: 20220064035
    Abstract: A bio-trickling filter box device capable of purifying organic wastewater and generating electricity is provided, which includes battery component(s) and a bio-trickling filter box component. The battery component(s) is provided in the bio-trickling filter box. The other end of each of trickling filter tube(s) is connected with a water tank. A water pump operates to make water flow through the trickling filter tube(s), pass through leakage holes and trickling holes, and drip into the battery component(s) in a water-drop manner, so as to supply an electric apparatus component with power. The bio-trickling filter box component(s) and the battery component(s) are combined, and the long-term impingement of water droplets on the battery component(s) can accumulate electric charge and generate the electricity. so as to provide power required by the electric apparatus component, which forms a biological treatment system that generates the power while treating the wastewater.
    Type: Application
    Filed: August 2, 2021
    Publication date: March 3, 2022
    Applicant: Sanming University
    Inventors: Chih-Hung WU, Xiang WANG, Jer-Yuan SHIH, Ching-Hua LIAO, Hongduo LI, Bin OUYANG, Zhigang WU, Lingwei YANG, Tingliang LIU
  • Patent number: 11232950
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 25, 2022
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.
    Inventors: Jheng Hao Fang, Yu Li Tsai, Hsueh-Hui Yang, Chih Hung Wu, Hwen Fen Hong
  • Publication number: 20210314315
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Publication number: 20210105269
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Application
    Filed: November 25, 2020
    Publication date: April 8, 2021
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Patent number: 10880296
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: December 29, 2020
    Assignee: KINGSTON DIGITAL INC.
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Publication number: 20200343093
    Abstract: The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: October 29, 2020
    Inventors: JHENG HAO FANG, YU LI TSAI, HSUEH-HUI YANG, CHIH HUNG WU, HWEN FEN HONG
  • Publication number: 20190164753
    Abstract: The present invention provides a method for fabricating an InGaP epitaxial layer by metal organic chemical vapor deposition (MOCVD). The method comprises: placing a silicon substrate in a reaction chamber; arranging the reaction chamber to have a first chamber temperature, and growing a first GaP layer with a first thickness on the Si substrate at the first chamber temperature; arranging the reaction chamber to have a second chamber temperature, and growing a second GaP layer with a second thickness on the first GaP layer at the second chamber temperature; arranging the reaction chamber to have a third chamber temperature for a first time interval, and then arranging the reaction chamber to have a fourth chamber temperature for a second time interval; and growing a multi-layered InGaP layer on the second GaP layer.
    Type: Application
    Filed: March 19, 2018
    Publication date: May 30, 2019
    Inventors: Wen-Hsiang Huang, Chih-Hung Wu, Hwen-Fen Hong
  • Patent number: 10304678
    Abstract: The present invention provides a method for fabricating an InGaP epitaxial layer by metal organic chemical vapor deposition (MOCVD). The method comprises: placing a silicon substrate in a reaction chamber; arranging the reaction chamber to have a first chamber temperature, and growing a first GaP layer with a first thickness on the Si substrate at the first chamber temperature; arranging the reaction chamber to have a second chamber temperature, and growing a second GaP layer with a second thickness on the first GaP layer at the second chamber temperature; arranging the reaction chamber to have a third chamber temperature for a first time interval, and then arranging the reaction chamber to have a fourth chamber temperature for a second time interval; and growing a multi-layered InGaP layer on the second GaP layer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 28, 2019
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C
    Inventors: Wen-Hsiang Huang, Chih-Hung Wu, Hwen-Fen Hong
  • Publication number: 20180288050
    Abstract: Security functions for a memory corresponding to a smart security storage may be facilitated or executed through operation of utility application corresponding to a smart device. For example, encryption/decryption of data stored on the memory may be facilitated or executed by a security module under control of an access application corresponding to the smart device. Data securely stored on the memory may be explored and accessed by the smart device or a host computing device under control of the access application.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Ben Wei Chen, Chih-Hung Wu
  • Patent number: 10069234
    Abstract: A portable data transmitting device, including a storage portion and a movable portion, is disclosed. The storage portion includes a fixed housing including a first side and a second side, and a first plug connector disposed on the first side. The movable portion includes a rotatable housing that is rotatably disposed on the second side of the fixed housing, a slidable housing that includes a first side and is slidably disposed on the rotatable housing, and a second plug connector disposed on the first side of the slidable housing. Thereby, the portable data transmitting device can be attached to portable apparatuses with different thicknesses, and can abut on the portable apparatus so as not to wobble or be bent easily.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: September 4, 2018
    Assignee: Kingston Digital, Inc.
    Inventors: Ben Wei Chen, Hsien-Chih Chang, Yi Ting Lin, Chih-Hung Wu
  • Patent number: 9953122
    Abstract: An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Jen Chang, Kuo-Nan Yang, Jui-Jung Hsu, Chih-Hung Wu, Chung-Hsing Wang
  • Patent number: 9946294
    Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 17, 2018
    Assignee: Faraday Technology Corp.
    Inventor: Chih-Hung Wu
  • Publication number: 20180069340
    Abstract: A portable data transmitting device, including a storage portion and a movable portion, is disclosed. The storage portion includes a fixed housing including a first side and a second side, and a first plug connector disposed on the first side. The movable portion includes a rotatable housing that is rotatably disposed on the second side of the fixed housing, a slidable housing that includes a first side and is slidably disposed on the rotatable housing, and a second plug connector disposed on the first side of the slidable housing. Thereby, the portable data transmitting device can be attached to portable apparatuses with different thicknesses, and can abut on the portable apparatus so as not to wobble or be bent easily.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 8, 2018
    Inventors: Ben Wei CHEN, Hsien-Chih CHANG, Yi Ting LIN, Chih-Hung WU
  • Publication number: 20180018410
    Abstract: An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: YU-JEN CHANG, KUO-NAN YANG, JUI-JUNG HSU, CHIH-HUNG WU, CHUNG-HSING WANG