Abstract: A structure of an optical switch makes the optical switch capable of receiving broadband signals. And the manufacturing procedure is simplified.

Abstract: A wafer stacked on a mounting layer is safely diced. The mounting layer has holes partially corresponding to chips on the wafer. Thus, chips obtained after dicing the wafer can be safely removed from the mounting tape. An amount of the mounting tape used can be reduced. And a production cost can be lowered as well.

Abstract: A wafer clamp according to the present invention always firmly clamps a wafer. A supporting arm of the wafer clamp will be replaced with a different one according to the wafer size. Moreover, with a larger area of the supporting arm, a wear resistance and a smoothness of the wafer is improved. Besides, the wafer clamp stops the wafer from slipping.

Abstract: An apparatus for integrated input/output circuit and a verification method thereof are provided. The apparatus effectively reduces the chip area occupation and cost, and decreases the resistance on an electrical transmission path of the integrated input/output circuit to improve the circuit efficiency. The apparatus comprises a metal structure and a plurality of integrated circuit components. Wherein, the integrated circuit comprises the integrated circuit components and the metal structure that has a bonding pad. In addition, the integrated circuit components are disposed directly under the metal structure and coupled to the metal structure. In which, the metal structure provides an electrical transmission path for the integrated circuit.

Abstract: A yield analysis method. First, a wafer having multiple dies is inspected to obtain wafer defect data containing defect information for every die in the wafer. Then a wafer map and an overall yield are generated according to the wafer defect data. The wafer map displays defective dies and defect-free dies in the wafer. Then, first and second systematic limited yields are calculated in accordance with the wafer defect data and the wafer map, wherein the first systematic limited yield is calculated excluding defective dies with localized distribution, and the second systematic limited yield is calculated excluding defective dies with repeated distribution. Then a random defect limited yield is determined in accordance with the overall yield, the first systematic limited yield, and the second systematic limited yield.

Abstract: A system implementing functionality adjustment for a portable electronic device. A portable electronic device has an interface, a function module, and a controller. The interface communicates with a host. The function module provides functionality. The controller sends identification information of the portable electronic device to the host and receives a first command from the host via the interface, and disables the function module in response to the first command. The host provides a functionality setting specifying a prohibited function for the portable electronic device, receives identification information from the portable electronic device, and sends a first command to the portable electronic device via the interface, wherein the first command, when executed by the portable electronic device, causes prohibited function thereof to be disabled according to the functionality setting.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: The present invention is related to a method for fabricating an imprint mold which can be used in the field of nano-imprint lithography. Firstly, a diamond film and a photoresist film are successively formed onto a substrate; wherein the photoresist film is more capable of anticorrosion than the diamond film. Then an energy beam lithography system is provided to make the photoresist film form a photoresist mask with particularly arranged patterns. Because of the etching selectivity between the diamond film and the photoresist film, on the surface of the diamond film a pattern can be easily formed with recessions and protrusions according to the photoresist mask by dry etching method.

Abstract: A structure of an optical switch makes the optical switch capable of receiving broadband signals. And the manufacturing procedure is simplified.

Abstract: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

Abstract: An apparatus for integrated input/output circuit and a verification method thereof are provided. The apparatus effectively reduces the chip area occupation and cost, and decreases the resistance on an electrical transmission path of the integrated input/output circuit to improve the circuit efficiency. The apparatus comprises a metal structure and a plurality of integrated circuit components. Wherein, the integrated circuit comprises the integrated circuit components and the metal structure that has a bonding pad. In addition, the integrated circuit components are disposed directly under the metal structure and coupled to the metal structure. In which, the metal structure provides an electrical transmission path for the integrated circuit.

Abstract: The present disclosure provides a system and method for recognizing a defect image associated with a semiconductor substrate. In one example, the method includes collecting defect data of the defect image by testing and measuring the semiconductor substrate, extracting a pattern from the defect data, normalizing a location, orientation, and size of the pattern, and identifying the pattern after the pattern is normalized.

Abstract: A solar cell with a superlattice structure and a fabricating method thereof are provided, which includes fabricating a superlattice structure of GaAsN/GaInAs, GaAsN/GaSbAs, or GaAsN/GaInSbAs between a base and an emitter of a middle cell of a triple junction solar cell by a strain-compensation technology. The provided solar cell not only decreases crystalline defects and increases the critical thickness of the crystal, but also makes the energy bandgap of GaAsN and GaInAs reach around the energy of 1.0 eV (electron volt). Hence, the absorption region can be raised to around the energy of 1.0 eV to enhance the efficiency of the solar cell.

Abstract: This invention discloses an apparatus and a method for a primitive filter. The primitive filter apparatus is used in graphic process and is applied in Graphic Process Unit. The primitive filter apparatus at least comprises a storage unit and a filter unit. The storage unit stores a plurality of input primitives. The filter unit couples to the storage unit and processes the stored of the plurality of input primitives, the function of the filter unit 32 is to drop or select the stored of the plurality of input primitives based on at least one predetermination. The storage unit further comprises a controller and a data buffer. The filter unit comprises an arithmetic logic unit and a determination unit. The at least one predetermination is a condition: the primitive filter apparatus drops the stored of the plurality of input primitives if does not cover any pixels.

Abstract: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

Abstract: An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.

Abstract: A base body comprises two frames to put lens and solar cells. The working process is simple and the weight and the cost of the base body is reduced.

Abstract: A programmable level shifter. The programmable level shifter comprises a first P-type FET, a first N-type FET, a second P-type FET, a second N-type FET, and a programmable device. The first P-type FET is coupled between a fist power line and a non-inverted output node, and a gate pole thereof is coupled to a inverted output node. The first N-type FET is coupled between the first P-type FET and a second power line. The programmable device is coupled between the first power line and the non-inverted output node, which can be programmed to change an effective resistance between the first power line and the inverted output node when the second P-type FET is turned on.

Abstract: An electrostatic discharge (ESD) protection circuit for protecting an input/output (I/O) circuit provided with different supply voltages against electrostatic discharge. The ESD protection circuit comprises a stacked NMOS transistor configuration, a triggering circuit and a disabling circuit. The ESD protection circuit is effectively disabled by the disabling circuit during normal operation. During an ESD event, a trigger current is generated by the triggering circuit to turn on the stacked NMOS transistor configuration and thus the ESD current is directed away. The ESD protection circuit also allows different voltages to be supplied during normal operation without damaging the transistors in the ESD protection circuit.

Abstract: A computer-implemented method and system for identifying process steps for purposes of queue-time control and abnormality detection is provided. In one example, the method includes retrieving manufacturing information associated with a fabrication process, where the manufacturing information includes multiple process step pairs. The manufacturing information may be divided into at least a high group and a low group using a statistical clustering method. Values, such as P-values, may then be calculated for each process step pair by applying a non-parametric statistical method to the high and low groups. The process step pairs may be ranked based on their calculated values, and redundant process step pairs may be eliminated. The remaining process step pairs may then be analyzed to identify a particular process step or process step pair.