Patents by Inventor Chih-Kang Yeh

Chih-Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180129414
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.
    Type: Application
    Filed: December 26, 2016
    Publication date: May 10, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9880742
    Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: selecting a first physical erasing unit, and loading a first logical address-physical address mapping table according to a physical address-logical address mapping table. The method also includes: updating the first logical address-physical address mapping table according to the physical address-logical address mapping table, and identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table and the first logical address-physical address mapping table. The method further includes: storing the first logical address-physical address mapping table, copying the valid data to a second physical erasing unit, and performing an erasing operation for the first physical erasing unit.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: January 30, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20180006669
    Abstract: A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.
    Type: Application
    Filed: August 22, 2016
    Publication date: January 4, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20170365334
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 21, 2017
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Po-Yung Chang
  • Patent number: 9830077
    Abstract: A data writing method for a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same are provided. The method includes grouping physical erasing units of the rewritable non-volatile memory module into a temporary area and a storage area. The method also includes selecting a first physical erasing unit from the temporary area, copying a plurality of valid data of the first physical erasing unit to a second physical erasing unit of the temporary area, and performing an erasing operation on the first physical erasing unit. The method further includes selecting a third physical erasing unit from the temporary area, copying a plurality of valid data of the third physical erasing unit to a forth physical erasing unit of the storage area, and performing the erasing operation on the third physical erasing unit.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 28, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20170322727
    Abstract: A trim command processing method for a memory storage apparatus having a rewritable non-volatile memory module having a plurality of physical programming units is provided. The method includes receiving a command from a host system; starting a trim operation to perform an operation corresponding to a trim command according to a record related to the trim command in a trim table if an operation corresponding the command is performed on the rewritable non-volatile memory module with a first mode; and not starting aforesaid trim operation if the operation corresponding the command is performed on the rewritable non-volatile memory module with a second mode.
    Type: Application
    Filed: June 20, 2016
    Publication date: November 9, 2017
    Inventor: Chih-Kang Yeh
  • Publication number: 20170315925
    Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.
    Type: Application
    Filed: June 16, 2016
    Publication date: November 2, 2017
    Inventor: Chih-Kang Yeh
  • Patent number: 9778862
    Abstract: A data storing method for storing data in a rewritable non-volatile memory module is provided. The method includes temporarily storing first data into a buffer memory; and starting a flush operation to write the first data from the buffer memory into a first physical programming unit. The method further includes determining whether the first physical programming unit is a lower physical programming unit; and if yes, writing second data into a second physical programming unit, wherein the second physical programming unit belongs to an upper physical programming unit, and the second physical programming unit and the first physical programming unit are formed by the same memory cells disposed on the same word line. Accordingly, the method can effectively prevent the data written during the flush operation from losing due to the programming fail occurred on other physical programming units.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 3, 2017
    Assignee: PHILSON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9773565
    Abstract: A memory retry-read method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a sequence of several retry-read parameter groups according to several weights of the retry-read parameter groups; reading data from a physical programming unit according to a read voltage; if the data are unable to be corrected by a corresponding ECC code, choosing an adjustment retry-read parameter group from the retry-read parameter groups; retrying reading new data from the physical programming unit according to the adjustment retry-read parameter group; if the new data are able to be corrected by the corresponding ECC code, determining the adjustment retry-read parameter group to be an available retry-read parameter group; and adjusting the weight of the available retry-read parameter group.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 26, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9690490
    Abstract: A method for writing data, a memory storage device and a memory control circuit unit are provided. The method includes receiving a write command and first data corresponding to the write command, obtaining initial data transmission information of the first data and determining whether the initial data transmission information conforms to a predetermined condition, compressing the first data to second data and writing the second data into a rewritable non-violate memory module if the initial data transmission information conforms to the predetermined condition, and writing the uncompressed first data into the rewritable non-violate memory module if the initial data transmission information does not conform to the predetermined condition.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: June 27, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Li-Chun Liang
  • Publication number: 20170154656
    Abstract: A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.
    Type: Application
    Filed: January 18, 2016
    Publication date: June 1, 2017
    Inventor: Chih-Kang Yeh
  • Patent number: 9652330
    Abstract: A method for data management and a memory storage device and a memory control circuit unit thereof. The method includes: configuring a NVRAM and a VRAM; storing first data which includes writing data from a host system in the NVRAM; storing second data read from a rewritable non-volatile memory module in the VRAM; when the memory storage device is re-powered on after power failure, reading the first data from the NVRAM, so as to write the writing data into the rewritable non-volatile memory module.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 16, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9619380
    Abstract: A data writing method for a memory storage apparatus having a first buffer memory, a second buffer memory and a rewritable non-volatile memory module is provided, and the transmission bandwidth of the first buffer memory is larger than the transmission bandwidth of the second buffer memory. The method includes: receiving a write command and first data thereof; determining whether the first data belongs to the successive big data; if the first data belongs to the successive big data, temporarily storing the first data into a first data buffer area of the first buffer memory, writing the first write data from the first data buffer area to the rewritable non-volatile memory module; and if the first data does not belongs to the successive big data, temporarily storing the first data into a second data buffer area of the second buffer memory.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 11, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9613705
    Abstract: In an exemplary embodiment, the method includes: determining whether a used capacity of first physical units initially configured to be programmed based on a first programming mode reaches a preset capacity and whether specific data stored in the first physical units matches a preset condition; and if the used capacity of the first physical units reaches the preset capacity and the specific data stored in the first physical units matches the preset condition, selecting at least one physical unit from second physical units initially configured to be programmed based on a second programming mode, and programming the selected physical unit based on the first programming mode. Accordingly, the writing speed decreased by the fully written buffer area may be improved.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 4, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9600363
    Abstract: A data accessing method for a memory storage apparatus is provided. The method includes using a first check code circuit to generate a first check code corresponding to a first data stream and generating a first data set based on the first data stream and the first check code. The method also includes using a second check code circuit to obtain the first data stream and the first check code from the first data set and check the first data stream according to the first check code. The method still includes using a third check code circuit to generate a second check code according to the checked first data stream and generating a data frame based on the checked first data stream and the second check code and thereby programming the data frame into a physical programming unit.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: March 21, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chang-Guang Lin
  • Patent number: 9582416
    Abstract: A data erasing method for a rewritable non-volatile memory module is provided. The method includes receiving a predetermined command for performing on a first logical sub-unit from a host system; marking a first physical programming unit mapped to the first logical sub-unit as being in an invalid data status and recording a mark for a first physical erasing unit that the first physical programming unit belongs to, in response to the predetermined command. The method further includes selecting the first physical erasing unit according to the mark, copying valid data in the first physical erasing unit to a second physical erasing unit gotten from a spare area of the rewritable non-volatile memory module and erasing data stored in the first physical erasing unit.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 28, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20170052704
    Abstract: The disclosure provides a memory management method, which includes: selecting at least one logical unit mapped to physical units programmed based on a first operating mode; determining a reference count according to a number of the selected logical unit; receiving a first write command; determining whether the reference count is greater than a threshold value; if the reference count is greater than the threshold value, programming first data into a first physical unit based on the first operating mode, and each memory cell in the first physical unit stores a first number of bit data; if the reference count is not greater than the threshold value, programming the first data into a second physical unit based on a second operating mode, and each memory cell in the second physical unit stores a second number of bit data, and the second number is greater than the first number.
    Type: Application
    Filed: September 15, 2015
    Publication date: February 23, 2017
    Inventor: Chih-Kang Yeh
  • Publication number: 20170039141
    Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a write command; recording physical-to-logical mapping information of write data corresponding to the write command into a first mapping table in a buffer memory; storing the physical-to-logical mapping information of the write data into a physical unit in a rewritable non-volatile memory module according to the first mapping table; updating the physical-to-logical mapping information of the write data recorded in the first mapping table, where the updated physical-to-logical mapping information only includes partial information of the physical-to-logical mapping information; and updating a second mapping table according to the updated physical-to-logical mapping information recorded in the first mapping table. Accordingly, the usage space of the first mapping table may be saved.
    Type: Application
    Filed: September 2, 2015
    Publication date: February 9, 2017
    Inventors: Chih-Kang Yeh, Yi-Hsien Lin
  • Publication number: 20170038977
    Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: selecting a first physical erasing unit, and loading a first logical address-physical address mapping table according to a physical address-logical address mapping table. The method also includes: updating the first logical address-physical address mapping table according to the physical address-logical address mapping table, and identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table and the first logical address-physical address mapping table. The method further includes: storing the first logical address-physical address mapping table, copying the valid data to a second physical erasing unit, and performing an erasing operation for the first physical erasing unit.
    Type: Application
    Filed: October 1, 2015
    Publication date: February 9, 2017
    Inventor: Chih-Kang Yeh
  • Patent number: 9563498
    Abstract: A method for preventing read-disturb errors, a memory storage apparatus and a memory control circuit unit are provided. The method includes counting an operation numerical value when receiving an operation command from the host system, wherein a first physical erasing unit is selected for executing the operation command. The method also includes selecting a second physical erasing unit and reading data from the second erasing unit. The method further includes determining whether a data error occurs at the second physical erasing unit according to the data read from the second physical erasing unit, and if the data error occurs, selecting a third physical erasing unit, correcting the data read from the second physical erasing unit to generate corrected data and writing the corrected data into the third physical erasing unit.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 7, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh