Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.

Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.

Abstract: A full-bridge resonant conversion circuit comprises a full-bridge rectification unit, a resonant unit, a first transformer, a second transformer and a synchronous rectification unit, wherein the full-bridge rectification unit comprises a first connection end and a second connection end, the resonant unit comprises a first resonant inductor, a resonant capacitor and a second resonant inductor, the resonant capacitor is connected in series with the first resonant inductor or the second resonant inductor. The first transformer comprises a first primary winding connected in series with the first resonant inductor, and a first secondary winding. Also, the second transformer comprises a second primary winding connected in series with the first primary winding and connected with the second resonant inductor, and a second secondary winding connected in parallel with the first secondary winding, and the synchronous rectification unit is connected with the first secondary winding and the second secondary winding.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a first inter metal dielectric (IMD) layer, a second inter metal dielectric layer and a third inter metal dielectric layer sequentially arranged on the substrate. The first inter metal dielectric layer includes at least one first wire, the second inter metal dielectric layer includes at least one mask layer, and the third inter metal dielectric layer includes at least one third wire and a super via. The super via penetrates through the second inter metal dielectric layer, and electrically connect to the first wire and the third wire, and part of the super via directly contacts the mask layer in the second inter metal dielectric layer.

Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a capacitor structure, a conductive contact, and a hard mask layer. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer. The conductive contact is disposed on the capacitor structure. The hard mask layer laterally surrounds the conductive contact. The conductive contact protrudes from a top surface of the hard mask layer.

Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

Abstract: A method includes providing a substrate having an n-type fin-like field-effect transistor (NFET) region and forming a fin structure in the NFET region. The fin structure includes a first layer having a first semiconductor material, and a second layer under the first layer and having a second semiconductor material different from the first semiconductor material. The method further includes forming a patterned hard mask to fully expose the fin structure in gate regions of the NFET region and partially expose the fin structure in at least one source/drain (S/D) region of the NFET region. The method further includes oxidizing the fin structure not covered by the patterned hard mask, wherein the second layer is oxidized at a faster rate than the first layer. The method further includes forming an S/D feature over the at least one S/D region of the NFET region.

Abstract: A fan driving circuit with temperature compensation comprises a power input end, a power output end connected with a fan motor, a first transistor arranged between the power input end and the power output end, a signal adjuster connected with the first transistor and connected with a signal generating circuit, a second transistor connected with the signal adjuster, and a feedback unit. The feedback unit comprises a first resistor and a second resistor connected in series, and a compensation bypass connected in parallel with the first resistor or the second resistor, wherein the compensation bypass comprises a thermistor, a resistance of the thermistor changes along with the temperature and changes a magnitude of a feedback current which is provided to the second transistor, so as to compensate a change of a common emitter current gain in the second transistor generated by the temperature.

Abstract: An optical element including a first substrate, a second substrate, a first optical film, a second optical film, and a spacer is provided. The first optical film is disposed on the first substrate and has a first surface and a plurality of first optical microstructures. The first optical microstructures are disposed on the first surface. The second optical film is disposed on the second substrate and has a second surface and a plurality of second optical microstructures. The second surface is opposite to the first surface. The second optical microstructures are disposed on the second surface. The orthogonal projection of the first optical microstructures on the first substrate does not overlap with the orthogonal projection of the second optical microstructures on the first substrate. The spacer is disposed between the first substrate and the second substrate. A wafer level optical module adopting the optical element is also provided.

Abstract: An optical element including a substrate, a first optical film and a second optical film. The first optical film and the second optical film are disposed on at least one side of the substrate and are both formed on the substrate. The first optical film has a first surface facing away from the substrate and a plurality of first optical microstructures disposed on the first surface. The second optical film has a second surface facing away from the substrate and a plurality of second optical microstructures disposed on the second surface. The orthogonal projection of the first optical microstructures on the substrate does not overlap the orthogonal projection of the second optical microstructures on the substrate. A wafer level optical module adopting the optical element is also provided.

Abstract: Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a semiconductor device includes a substrate comprising a first fin and a second fin. A first epitaxial fin is disposed over the first fin, and a second epitaxial fin is disposed over the second fin. The second fin is proximate the first fin. The first epitaxial fin and the second epitaxial fin have an upper portion with a substantially pillar shape.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.

Abstract: The optical component includes a first substrate, a first diffractive layer formed on the first substrate, a second substrate, a second diffractive layer formed on the second substrate, and a bonding material disposed between the first substrate and the second substrate and connecting the first substrate and the second substrate. The second diffractive layer is disposed opposite to the first diffractive layer, and both the first diffractive layer and the second diffractive layer are located between the first substrate and the second substrate. A gap is formed between the first diffractive layer and the second diffractive layer.