Patents by Inventor Chih-Yu Chang

Chih-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory array contact structures
    Patent number: 11653500
    Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Chang, Meng-Han Lin, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin
  • WIDE-BANDGAP SEMICONDUCTOR LAYER CHARACTERIZATION
    Publication number: 20230050640
    Abstract: A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.
    Type: Application
    Filed: January 6, 2022
    Publication date: February 16, 2023
    Inventors: Chih-Yu CHANG, Ken-Ichi GOTO, Yen-Chieh HUANG, Min-Kun DAI, Han-Ting TSAI, Sai-Hooi YEONG, Yu-Ming LIN, Chung-Te LIN
  • Memory cell and method of operating the same
    Patent number: 11568912
    Abstract: A memory cell includes a write bit line, a write transistor and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Chih-Yu Chang, Yu-Ming Lin
  • Metal insulator metal (MIM) structure and manufacturing method thereof
    Patent number: 11563079
    Abstract: A MIM structure and manufacturing method thereof are provided. The MIM structure includes a substrate having a first surface and a metallization structure over the substrate. The metallization structure includes a bottom electrode layer, a dielectric layer on the bottom electrode layer, a ferroelectric layer on the dielectric layer, a top electrode layer on the ferroelectric layer, a first contact electrically coupled to the top electrode layer, and a second contact penetrating the dielectric layer and the ferroelectric layer, electrically coupled to the bottom electrode layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sai-Hooi Yeong, Chih-Yu Chang, Chun-Yen Peng, Chi On Chui
  • Memory Array Gate Structures
    Publication number: 20220416085
    Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 29, 2022
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Organic light-emitting device
    Patent number: 11522151
    Abstract: An organic light-emitting device includes a first electrode layer, an emission layer, an electron transporting layer, an electron injection layer, and a second electrode layer sequentially formed from bottom to top. The emission layer includes a guest light-emitting material, a first phenyl phosphine oxide derivative and a hole transporting material. The electron transporting layer includes a second phenyl phosphine oxide derivative and a third phenyl phosphine oxide derivative different from the second phenyl phosphine oxide derivative. One of the second phenyl phosphine oxide derivative and the third phenyl phosphine oxide derivative is identical to the first phenyl phosphine oxide derivative. The electron injection layer includes an alkaline metal compound.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: December 6, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsin-Fei Meng, Sheng-Fu Horng, Yu-Chiang Chao, Chih-Yu Chang, Yu-Fan Chang, Mei-Peng Liou, Qian-Wei Lin, Hsiao-Tso Su, Chiung-Wen Chang
  • Memory device and method of fabricating the memory device
    Patent number: 11522046
    Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang
  • Memory Array Contact Structures
    Publication number: 20220384348
    Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Yu Chang, Meng-Han Lin, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin
  • Memory Array Including Epitaxial Source Lines and Bit Lines
    Publication number: 20220384484
    Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Chi On Chui, Yu-Ming Lin
  • Ferroelectric memory device and method of forming the same
    Patent number: 11515332
    Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • Embedded ferroelectric FinFET memory device
    Patent number: 11508753
    Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang, Han-Jong Chia
  • SEMICONDUCTOR DEVICE WITH NEGATIVE CAPACITANCE STRUCTURE
    Publication number: 20220367724
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a first negative capacitance material, and an isolation structure formed over the substrate. The semiconductor device structure includes a gate structure formed over the fin structure, and a source feature and a drain feature formed over the fin structure. An interface between the fin structure and the source feature is lower than a top surface of the isolation structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng YOUNG, Chih-Yu CHANG, Sai-Hooi YEONG, Chi-On CHUI, Chih-Hao WANG
  • FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20220359570
    Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Chih-Yu Chang
  • EMBEDDED FERROELECTRIC FINFET MEMORY DEVICE
    Publication number: 20220352184
    Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Bo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang, Han-Jong Chia
  • Semiconductor device with negative capacitance structure and method for forming the same
    Patent number: 11469324
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first negative capacitance material over a substrate and patterning the first negative capacitance material to form a fin structure over the substrate. The method also includes forming a source feature and a drain feature in and protruding from a source region and a drain region of the fin structure. The method also includes forming a gate dielectric structure between the source feature and the drain feature to cover a channel region of the fin structure and forming a gate electrode layer over the gate dielectric structure.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi-On Chui, Chih-Hao Wang
  • THREE-DIMENSIONAL MEMORY DEVICE AND METHOD
    Publication number: 20220285393
    Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 8, 2022
    Inventors: Bo-Feng Young, Meng-Han Lin, Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin
  • Negative Capacitance Transistor Having A Multilayer Ferroelectric Structure Or A Ferroelectric Layer With A Gradient Doping Profile
    Publication number: 20220285521
    Abstract: A negative capacitance semiconductor device includes a substrate. A dielectric layer is disposed over a portion of the substrate. A ferroelectric structure disposed over the dielectric layer. Within the ferroelectric structure: a material composition of the ferroelectric structure varies as a function of a height within the ferroelectric structure. A gate electrode is disposed over the ferroelectric structure.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Chih-Yu Chang, Ching-Wei Tsai, Kuan-Lun Cheng
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220278117
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 1, 2022
    Inventors: CHIH-YU CHANG, SAI-HOOI YEONG, YU-MING LIN, CHIH-HAO WANG
  • FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH OXIDE SEMICONDUCTOR CHANNEL
    Publication number: 20220270872
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a stack over a substrate. The stack has multiple sacrificial layers and multiple oxide semiconductor layers laid out alternately. The method also includes partially removing the sacrificial layers to expose inner portions of the oxide semiconductor layers. The inner portions of the oxide semiconductor layers form multiple oxide semiconductor nanostructures. The method further includes changing an atomic concentration of oxygen of the oxide semiconductor nanostructures. In addition, the method includes forming a gate stack wrapped around one or more of the oxide semiconductor nanostructures after the changing of the atomic concentration of oxygen of the oxide semiconductor nanostructures.
    Type: Application
    Filed: May 12, 2022
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu CHANG, Sai-Hooi YEONG, Yu-Ming LIN
  • TWO-DIMENSIONAL (2D) MATERIAL FOR OXIDE SEMICONDUCTOR (OS) FERROELECTRIC FIELD-EFFECT TRANSISTOR (FEFET) DEVICE
    Publication number: 20220246766
    Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 4, 2022
    Inventors: Mauricio Manfrini, Chih-Yu Chang, Sai-Hooi Yeong