Abstract: An oral cavity scanning device is provided in the invention. The oral cavity scanning device includes an image capturing unit, an IMU circuit and a processing unit. The image capturing unit obtains a first image and a second image. The IMU circuit obtains IMU information corresponding to the first image and the second image. The processing unit obtains a distance value between the first image and the second image. The processing unit uses a contour algorithm to obtain a first contour and a second contour. The processing unit obtains first sampling points according to the first contour and second sampling points according to the second contour. The processing unit uses a feature algorithm to find relative feature points between the first sampling points and the second sampling points. The processing unit uses a depth information algorithm to obtain the depth information of each feature point.

Abstract: A Rugged portable device comprises: a base, a cover pivotally connected to the base, a first antenna unit, a second antenna unit, and a control unit. The first antenna unit and the second antenna unit are respectively disposed at an edge of the cover and an edge of the base, and the first antenna unit and the second antenna unit respectively have a near-field antenna and a far-field antenna. When the cover pivots relative to the base and is close to the base, the near-field antenna disposed at the cover and the near-field antenna disposed at the base generate a near-field communication (NFC) sensing signal and the near-field communication sensing signal is transmitted to the control unit. Therefore, the control unit sets up one of functions in the rugged portable device. For instance, the control unit switches off and/or switches on the far-field antenna or a peripheral unit (a keyboard or a camera).

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: An interfacial layer is formed in a manner that enables a ferroelectric layer to be formed such that formation of ferroelectric crystalline phases (e.g., orthorhombic crystalline phases) in the ferroelectric layer is increased and formation of non-ferroelectric crystalline phases (e.g., monoclinic phases, tetragonal phases) in the ferroelectric layer is reduced. To achieve this, the grain size and/or other properties of the interfacial layer may be controlled during formation of the interfacial layer such that the grain size and/or other properties of the interfacial layer facilitate formation of a larger grain size in the ferroelectric layer. At larger grain sizes in the ferroelectric layer, the concentration of the ferroelectric crystalline phases in the crystal structure of the ferroelectric layer may be increased relative to if the ferroelectric layer were formed to a smaller grain size.

Abstract: A method includes: obtaining impact values for characteristic conditions; selecting training data subsets respectively from training data sets according to the impact values; obtaining a candidate model and an evaluation value based on the training data subsets; supplementing the training data subsets according to the impact values; obtaining another candidate model and another evaluation value based on training data subsets thus supplemented; repeating the step of supplementing the training data subset, and the step of obtaining another candidate model and another evaluation value based on the training data subsets thus supplemented; and selecting one of the candidate models as a prediction model based on the evaluation values.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: A p-aminobenzoic acid-producing microorganism is provided. The p-aminobenzoic acid-producing microorganism is obtained by a method for preparing a p-aminobenzoic acid-producing microorganism. The method for preparing a p-aminobenzoic acid-producing microorganism includes (a) performing an acclimation process on a source microorganism with at least one sulfonamide antibiotic to obtain at least one acclimatized microorganism and (b) screening out at least one p-aminobenzoic acid-producing microorganism from the at least one acclimatized microorganism, wherein the at least one p-aminobenzoic acid-producing microorganism has a higher p-aminobenzoic acid titer than the source microorganism.

Abstract: A display apparatus includes a light-transmitting structural plate, some optical microscopic structures, an optical film, a base plate and some light emitting elements. The light-transmitting structural plate has a first side and a second side opposite to each other. The optical microscopic structures are regularly arrayed and formed on the first side or the second side. The optical microscopic structure has an inclined surface connecting at a connecting line and forming an angle ranging between 30 degrees and 150 degrees with a corresponding inclined surface of an adjacent one of the optical microscopic structures. The optical film is located on the first side. The base plate is separated from the second side by a space. The light emitting elements are located inside the space and disposed on the base plate. The light emitting elements respectively emit a light ray to the light-transmitting structural plate.

Abstract: A calibration apparatus includes a processor, an alignment device, and an arm. The alignment device captures images in a three-dimensional space, and a tool is arranged on a flange of the arm. The processor records a first matrix of transformation between an end-effector coordinate-system and a robot coordinate-system, and performs a tool calibration procedure according to the images captured by the alignment device for obtaining a second matrix of transformation between a tool coordinate-system and the end-effector coordinate-system. The processor calculates relative position of a tool center point of the tool in the robot coordinate-system based on the first and second matrixes, and controls the TCP to move in the three-dimensional space for performing a positioning procedure so as to regard points in an alignment device coordinate-system as points of the TCP, and calculates the relative positions of points in the alignment device coordinate-system and in the robot coordinate-system.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.