Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A lock assembly includes a casing, a blocking unit, and a lock unit. The blocking unit includes a blocking member operable to move between an open position and a block position. The lock unit includes an engaging member, an electric unlock module, and a manual unlock module. The engaging member has a main body having first and second abutment portions, and is movable between an engaging position for engaging the blocking member when the blocking member is in the block position, and an unlocked position for disengaging from the blocking member. One of the electric unlock module and the manual unlock module is operable to abut a push member thereof against a corresponding one of the first and second abutment portions to linearly move the engaging member.

Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.

Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.

Abstract: A modified electrode, manufacturing method thereof and use thereof are provided. The manufacturing method includes steps of soaking a copper substrate in a solution to obtain a BiOI/copper(I) iodide, BiOI/copper(I) iodide/metallic bismuth, and copper(I) iodide/metallic bismuth composite modified electrodes by electroless plating method. The obtained electrodes, designated as bismuth-based modified electrode, can be used for the electrohydrodimerization of acrylonitrile to synthesize adiponitrile.

Abstract: A polishing layer is provided. The polishing layer have a surface pattern, a cross section of the surface pattern along a direction has a plurality of grooves and a plurality of polishing portions, each of the grooves is disposed between every two adjacent polishing portions, and the polishing layer comprises a body layer and a surface layer. The surface layer is disposed on a surface of the body layer, and a top of at least one of the polishing portions has at least one flattened region exposing the body layer.

Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

Abstract: A selector structure may include a bottom electrode including a bottom low thermal conductivity (LTC) metal and a first bottom high thermal conductivity (HTC) metal, a first switching film on the bottom electrode and having an electrical resistivity switchable by an electric field, and a first top electrode on the first switching film and including a first top low thermal conductivity (LTC) metal and a first top high thermal conductivity (HTC) metal.

Abstract: A phase change device includes a substrate with a top surface. A heater structure is disposed on the substrate. The heater structure has first and second sidewalls on opposite sides of the heater structure. A phase change element is disposed over the heater structure. The phase change element includes three connected portions. A first portion is disposed over the heater structure. A second portion is disposed over the first sidewall of the heater structure. A third portion is over a first portion of the top surface of the substrate adjacent to and spaced apart from the first sidewall of the heater structure.

Abstract: A semiconductor structure comprising a first electrode, a second electrode, a phase-change material (PCM) line in contact with and positioned between the first electrode and the second electrode, at least two heater lines positioned between the first electrode and the second electrode, and an isolation layer positioned between the PCM line and the at least two heater lines is provided. A method of forming a semiconductor structure is provided, the method including forming a dielectric isolation layer having a planar top surface over a substrate, forming at least two heater lines over the planar top surface, forming at least one heater-capping dielectric plate over the at least two heater lines, forming a phase-change material (PCM) line over the at least one heater-capping dielectric plate, forming a first electrode and a second electrode, and forming a PCM-capping dielectric plate over the PCM line.

Abstract: A memory device includes a memory array comprising memory cells associated with a plurality of wordlines control logic that is to perform operations including: causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors; and at least one of after the memory cells associated with the second wordline are programmed or after completion of programming the physical unit, causing the memory cells associated with the first wordline to be programmed.

Abstract: A phase-change material (PCM) switching device includes: a base dielectric layer over a semiconductor substrate; a first heater element disposed on the base dielectric layer, the first heater element comprising a first metal element characterized by a first coefficient of thermal expansion (CTE); a second heater element disposed on the first heater element, the second heater element comprising a second metal element characterized by a second CTE larger than the first CTE; a first metal pad and a second metal pad; and a PCM region comprising a PCM operable to switch between an amorphous state and a crystalline state in response to heat generated by the first heater element and the second heater element, wherein the PCM region is disposed above a top surface of the second heater element, and an air gap surrounds the first heater element and the second heater element from three sides.

Abstract: A container includes a container body and an air processing system. The container body includes a plurality of walls defining an interior space for receiving wafers. The air processing system is attached to the container body. The air processing system includes an exchange module, an air extraction module, a first contaminant removal module, a processing module, a second contaminant removal module, a controller module and a power module. The exchange module is coupled to one of the walls of the container body. The air extraction module extracts air from the container body. The first contaminant removal module is coupled to the air extraction module and the exchange module. The processing module is coupled to the air extraction module. The second contaminant removal module is coupled to the processing module and the exchange module. The controller module is configured to turn the air extraction module on and off.

Abstract: A phase-change material (PCM) switching device is provided. The PCM switching device includes: a base dielectric layer over a semiconductor substrate; a heater element embedded in the base dielectric layer, the heater element comprising a first metal element and configured to generate heat in response to a current flowing therethrough; a self-aligned dielectric layer disposed on the heater element, wherein the self-aligned dielectric layer comprises one of an oxide of the first metal element and a nitride of the first metal element, and the self-aligned dielectric layer is horizontally aligned with the heater element; a PCM region disposed on the self-aligned dielectric layer, wherein the PCM region comprises a PCM operable to switch between an amorphous state and a crystalline state in response to the heat generated by the heater element; and two metal pads electrically connected to the PCM region.

Abstract: A pyroelectric generator may be included in the same semiconductor device as a radio frequency (RF) switch (e.g., a phase-change material (PCM) RF switch and/or other types of RF switch). The pyroelectric generator includes a pyroelectric material layer between two electrodes. The pyroelectric generator is configured to scavenge thermal energy that is generated during the operation of the RF switch, and to convert the thermal energy into electrical energy that may be stored and reused.

Abstract: A composite material structure, including an outer layer, an inner layer, and a middle layer, is provided. The outer layer includes a metallic material. The inner layer includes a fiber material and a resin material. The outer layer has a first thickness, the inner layer has a second thickness, and the first thickness is different from the second thickness. The middle layer includes an adhesive material and is disposed between the outer layer and the inner layer. Two opposite surfaces of the middle layer are respectively in direct contact with the outer layer and the inner layer. A manufacturing method of the composite material structure is also provided.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.