Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line.

Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that a temperature associated with the memory device satisfies a threshold criterion; determining a memory access operation type of the memory access operation; and performing the memory access operation on the set of cells associated with the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the memory access operation type and the temperature associated with the memory device.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.

Abstract: A fan assembly including a fan frame and an impeller. The fan frame includes a frame body and a first peripheral protruding plate and has an air inlet and an air outlet. The first peripheral protruding plate protrudes from a side of the frame body and forms an air channel together with the frame body. The first peripheral protruding plate is configured to reduce a noise made by the fan assembly. The air inlet is in fluid communication with the air outlet via the air channel. The impeller is rotatably disposed on the frame body and located in the air channel. The protruding height of the first peripheral protruding plate relative to the frame body ranges from 50 to 100 percent of an overall axial thickness of the impeller.

Abstract: Provided are ferroelectric tunnel junction (FTJ) structures, memory devices, and methods for fabricating such structures and devices. An FTJ structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.

Abstract: A storage drive assembly is provided. The storage drive assembly includes a storage drive sized and shaped for insertion into a slot within a chassis, a latching mechanism coupled to a first end of the storage drive, the latching mechanism including an actuation component actuable to transition the latching mechanism from a locked state in which the latching mechanism restricts displacement of the storage drive relative to the chassis to an unlocked state in which the latching mechanism enables displacement of the storage drive assembly relative to the chassis, and a drive secure cover plate adapted to removably mate with the latching mechanism in the locked state, the mated drive secure cover plate preventing physical access to the actuation component.

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

Abstract: A load switch circuit is provided. The load switch circuit includes a control chip and a current limit protection circuit. The control chip is operated at a power supply voltage, configured to receive an input voltage, and controlled by an enable signal to provide an output voltage and an output current to a load. The current limit protection circuit is configured to provide a current limit control voltage to a current limit and low power pin of the control chip, so that the control chip may adjust a current limit of the output current.

Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: An antenna phase control method is applied to an antenna phase control device and an antenna, the antenna disposed on a moving carrier. The method includes obtaining a location information of the moving carrier; obtaining a destination information of the moving carrier and generating a navigation information according to the location information and the destination information; calculating at least one preset location point in the path and a phase information of the antenna corresponding to the at least one preset location point; and controlling a phase of the antenna according to the phase information when the moving carrier reaches the at least one preset location point. The present disclosure also provides an antenna phase control device.

Abstract: An antenna phase control method is applied to an antenna phase control device, the antenna disposed on a moving carrier to communicate with a satellite. The method includes obtaining an initial phase of the antenna, obtaining an instant rotation information of a steering wheel of the moving carrier and speed information of the moving carrier, calculating a compensation phase of the antenna according to the instant rotation information and the speed information, and adjusting the initial phase of the antenna according to the compensation phase. The present disclosure also provides an antenna phase control device. The present disclosure can calculate the antenna phase according to the direction information and the speed information of the moving carrier, so as to dynamically adjust the radiation direction of the antenna.

Abstract: A battery module including a battery frame, a plurality of locking structures, a plurality of battery units, and a plurality of lug structures is provided. The battery frame is provided with an accommodating space. The battery frame includes a first portion extending along a first direction and a second portion extending along a second direction. The first direction is different from the second direction. The locking structures are disposed on the battery frame. At least one of the plurality of locking structures is disposed on an outer side of each of the first portion and the second portion. The battery units are disposed in the accommodating space. Each of the lug structures includes a lock portion configured to detachably engage with one of the locking structures.