Abstract: In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate. The substrate includes a first semiconductor layer, a second semiconductor layer, and an insulating layer between the first semiconductor layer and the second semiconductor layer. The semiconductor device structure also includes a gate stack over the substrate. The semiconductor device structure further includes source and drain structures in the second semiconductor layer of the substrate. The source and drain structures are on opposite sides of the gate stack. In addition, the semiconductor device structure includes a first isolation feature in the substrate. The first isolation feature includes an insulation material and surrounds the source and drain structures. The semiconductor device structure also includes a second isolation feature in the first isolation feature. The second isolation feature includes a metal material and surrounds the source and drain structures.

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.

Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.

Abstract: In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

Abstract: The semiconductor structure includes a semiconductor substrate; a first active region and a second active region on the semiconductor substrate and separated by an isolation feature; and a field-effect transistor formed on the semiconductor substrate. The field-effect transistor further includes a gate stack disposed on the semiconductor substrate and extending from the first active region to the second active region; and a source and a drain formed on the first active region and interposed by the gate stack. The semiconductor structure further includes a doped feature formed on the second active region and configured as a gate contact to the field-effect transistor.

Abstract: A semiconductor wafer and a semiconductor wafer fabrication method are provided. The wafer includes a supporting substrate, a semiconductor substrate and a contact layer. The supporting substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate is disposed on the first surface of the supporting substrate, in which the semiconductor substrate is configured to form plural devices. The contact layer is disposed on the second surface of the supporting substrate to contact the supporting substrate, in which the contact layer is configured to contact an electrostatic chuck and has a resistivity of the contact layer smaller than a resistivity of the supporting substrate. In semiconductor wafer fabrication method, at first, a raw wafer is provided. Then, the contact layer is formed by using an implantation operation or a deposition operation.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate. The substrate includes a first semiconductor layer, a second semiconductor layer, and an insulating layer between the first semiconductor layer and the second semiconductor layer. The semiconductor device structure also includes a gate stack over the substrate. The semiconductor device structure further includes source and drain structures in the second semiconductor layer of the substrate. The source and drain structures are on opposite sides of the gate stack. In addition, the semiconductor device structure includes a first isolation feature in the substrate. The first isolation feature includes an insulation material and surrounds the source and drain structures. The semiconductor device structure also includes a second isolation feature in the first isolation feature. The second isolation feature includes a metal material and surrounds the source and drain structures.

Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.

Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.