Abstract: An integrated circuit structure or a back side illumination image sensor is provided, wherein the integrated circuit structure includes a bond pad and a metal structure located in a dielectric layer, wherein the bond pad and the metal structure have different materials, and the back side illumination image sensor includes an image sensor unit and an interconnect structure respectively located on both sides of a bond pad. Moreover, an integrated circuit process forming said integrated circuit structure or back side illumination image sensor is also provided.

Abstract: A semiconductor device includes a semiconductor substrate, a buried layer, a deep well having a first conductivity type being disposed on the buried layer, a first doped region having the first conductivity type and a well having the second conductivity type being disposed in the deep well, a first heavily doped region having the first conductivity type being disposed in the first doped region, a second heavily doped region having the first conductivity type being disposed in the well, a gate disposed between the first heavily doped region and the second heavily doped region, and a first trench structure and a second trench structure being disposed at the two sides of the gate in the semiconductor substrate. The first trench structure contacts the buried layer, and a depth of the second trench structure is substantially larger than a depth of the buried layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. A semiconductor structure includes a device substrate, a conductive film, a dielectric film and a conductive plug. The device substrate includes a semiconductor substrate and a conductive structure on an active surface of the semiconductor substrate. The device substrate has a substrate opening passing through the semiconductor substrate and exposing the conductive structure. The conductive film, the conductive plug and the dielectric film between the conductive film and the conductive plug are disposed in the substrate opening.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. A semiconductor structure includes a device substrate, a conductive film, a dielectric film and a conductive plug. The device substrate includes a semiconductor substrate and a conductive structure on an active surface of the semiconductor substrate. The device substrate has a substrate opening passing through the semiconductor substrate and exposing the conductive structure. The conductive film, the conductive plug and the dielectric film between the conductive film and the conductive plug are disposed in the substrate opening.

Abstract: A stacked wafer structure includes a CIS wafer, an ISP wafer, a lamination layer, a through silicon via and a pixel device. The CIS wafer bonds to the ISP wafer through the lamination layer. The pixel device is disposed on the CIS wafer. The through silicon via penetrates either the CIS wafer or the ISP wafer to connect devices in CIS wafer to the devices in ISP wafer electrically.

Abstract: A stacked wafer structure includes a CIS wafer, an ISP wafer, a lamination layer, a through silicon via and a pixel device. The CIS wafer bonds to the ISP wafer through the lamination layer. The pixel device is disposed on the CIS wafer. The through silicon via penetrates either the CIS wafer or the ISP wafer to connect devices in CIS wafer to the devices in ISP wafer electrically.

Abstract: A semiconductor structure and a method for forming the same are provided. The method comprises following steps. A gate material film is formed on a substrate in a first device region and a second device region. The gate material film in the first device region is patterned to form a first patterned gate. A first spacer material film containing a nitride material is formed on the first patterned gate in the first device region and the gate material film in the second device region. The first spacer material film and the gate material film are patterned in the second device region to form a second patterned gate.

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.

Abstract: An image sensor includes a substrate with a front side and a back side, the substrate having a sensor array region and a peripheral region defined thereon, a plurality of sensor device disposed in the sensor array region, a first metal layer disposed on the front sides within the peripheral region, a bonding pad disposed on the backside within the peripheral region, and at least a connecting element penetrating the substrate and substantially connect to the first metal layer and the bonding pad, wherein parts of the substrate is between the bonding pad and the first metal layer.

Abstract: An image sensor comprises a substrate, a plurality of photoelectric transducer devices, an interconnect structure, at least one dielectric isolator and a back-side alignment mark. The substrate has a front-side surface and a back-side surface opposite to the front-side surface. The interconnect structure is disposed on the front-side surface. The photoelectric transducer devices are formed on the front-side surface. The dielectric isolator extends downwards into the substrate from the back-side surface in order to isolate the photoelectric transducer devices. The back-side alignment mark extends downwards into the substrate from the back-side surface and references to a front-side alignment mark previously formed on the front-side surface.

Abstract: A method of forming trench isolation with different depths of a semiconductor device is disclosed. A semiconductor substrate having a first mask layer formed thereon is first provided. A first etching process is performed with the first mask layer as an etching mask to form a shallow trench structure, followed by forming a first dielectric layer on the semiconductor substrate to fill the shallow trench structure. The first dielectric layer is then patterned to form a second mask layer which is used in a second etching process to form a deep trench structure. After that, a dielectric material is applied to fill the deep trench structure.

Abstract: The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.

Abstract: A high voltage metal oxide semiconductor device with low on-state resistance is provided. A multi-segment isolation structure is arranged under a gate structure and beside a drift region for blocking the current from directly entering the drift region. Due to the multi-segment isolation structure, the path length from the body region to the drift region is increased. Consequently, as the breakdown voltage applied to the gate structure is increased, the on-state resistance is reduced.

Abstract: An image sensor includes a substrate with a front side and a back side, the substrate having a sensor array region and a peripheral region defined thereon, a plurality of sensor device disposed in the sensor array region, a first metal layer disposed on the front sides within the peripheral region, a bonding pad disposed on the backside within the peripheral region, and at least a connecting element penetrating the substrate and substantially connect to the first metal layer and the bonding pad, wherein parts of the substrate is between the bonding pad and the first metal layer.

Abstract: An integrated circuit structure or a back side illumination image sensor is provided, wherein the integrated circuit structure includes a bond pad and a metal structure located in a dielectric layer, wherein the bond pad and the metal structure have different materials, and the back side illumination image sensor includes an image sensor unit and an interconnect structure respectively located on both sides of a bond pad. Moreover, an integrated circuit process forming said integrated circuit structure or back side illumination image sensor is also provided.

Abstract: A semiconductor device includes a semiconductor substrate and at least a first gate structure disposed on the semiconductor substrate. Furthermore, a spacer only disposed at a side of the first gate structure, and a material of the spacer does not comprise nitride.

Abstract: The present disclosure provides a fabricating method of a semiconductor chip which includes the following steps. First, a substrate is provided. The substrate defines a memory unit region and a peripheral logic region. Then, a first spacer is formed around a stack structure of the memory unit region. The first space includes a first silicon oxide layer and the first silicon oxide layer directly contacts with the stack structure. After that, a silicon nitride layer is formed on both the first spacer and the peripheral logic region. Finally, the additional silicon nitride layer on the first spacer is removed but portions of the additional silicon nitride layer around gate structures in the peripheral logic region are remained.

Abstract: A semiconductor device includes a semiconductor substrate, a buried layer, a deep well having a first conductivity type being disposed on the buried layer, a first doped region having the first conductivity type and a well having the second conductivity type being disposed in the deep well, a first heavily doped region having the first conductivity type being disposed in the first doped region, a second heavily doped region having the first conductivity type being disposed in the well, a gate disposed between the first heavily doped region and the second heavily doped region, and a first trench structure and a second trench structure being disposed at the two sides of the gate in the semiconductor substrate. The first trench structure contacts the buried layer, and a depth of the second trench structure is substantially larger than a depth of the buried layer.

Abstract: A manufacturing method of a BSI image sensor includes providing a substrate having a plurality of photo-sensing elements and a plurality of multilevel interconnects formed on a first side of the substrate; forming a redistribution layer (RDL) and a first insulating layer covering the RDL on the front side of the substrate; providing a carrier wafer formed on the front side of the substrate; forming a color filter array (CFA) on a second side of the substrate, the second side being opposite to the first side; removing the carrier wafer; and forming a first opening in the first insulating layer for exposing the RDL.