Patents by Inventor Ching-Hung Kao

Ching-Hung Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10115758
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Publication number: 20180301496
    Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 18, 2018
    Inventors: Che-Chun Lu, Ching-Hung Kao, Fu-Cheng Chang, Chia-Pin Cheng, Po-Chun Chiu
  • Patent number: 10020265
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lee, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao
  • Publication number: 20180166476
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 14, 2018
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Publication number: 20180166481
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: May 10, 2017
    Publication date: June 14, 2018
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Patent number: 9997628
    Abstract: The present disclosure provides a semiconductor device and a method of fabricating the semiconductor device. In some embodiments, the semiconductor device includes a substrate having a well region, a first source/drain region, a second source/drain region, a buried channel and a gate structure. The first source/drain region is located within the well region. The gate structure includes a co-doped gate including polysilicon and having a first concentration of a n-type impurity and a second concentration of a p-type impurity, in which the n-type impurity and the p-type impurity are mixed and distributed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Jheng-Hong Jiang, Fu-Cheng Chang, Ching-Hung Kao, Hsin-Chi Chen
  • Publication number: 20180158851
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 7, 2018
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Publication number: 20180138218
    Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 17, 2018
    Inventors: Chia-Pin Cheng, Fu-Cheng Chang, Ching-Hung Kao, Che-Chun Lu
  • Patent number: 9887225
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Patent number: 9859328
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Publication number: 20170345852
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 30, 2017
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Publication number: 20170179037
    Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.
    Type: Application
    Filed: May 18, 2016
    Publication date: June 22, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung LEE, Chih-Fei LEE, Fu-Cheng CHANG, Ching-Hung KAO
  • Patent number: 9666473
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 30, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Publication number: 20170077170
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
    Type: Application
    Filed: November 22, 2016
    Publication date: March 16, 2017
    Inventor: Ching-Hung Kao
  • Patent number: 9543190
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well having a first conductivity type in the semiconductor substrate, wherein the deep well is disposed on the buried layer; forming a first trench structure in the deep well, wherein the first trench structure extends into the buried layer; and forming a second trench structure in the semiconductor substrate, wherein a depth of the second trench structure is larger than a depth of the buried layer.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: January 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Patent number: 9537040
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: January 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Publication number: 20160268159
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 15, 2016
    Inventor: Ching-Hung Kao
  • Patent number: 9406710
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: August 2, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Patent number: 9312292
    Abstract: A manufacturing method of a BSI image sensor includes providing a substrate having a plurality of photo-sensing elements and a plurality of multilevel interconnects formed on a first side of the substrate; forming a redistribution layer (RDL) and a first insulating layer covering the RDL on the front side of the substrate; providing a carrier wafer formed on the front side of the substrate; forming a color filter array (CFA) on a second side of the substrate, the second side being opposite to the first side; removing the carrier wafer; and forming a first opening in the first insulating layer for exposing the RDL.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Hung Kao
  • Publication number: 20150270162
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well having a first conductivity type in the semiconductor substrate, wherein the deep well is disposed on the buried layer; forming a first trench structure in the deep well, wherein the first trench structure extends into the buried layer; and forming a second trench structure in the semiconductor substrate, wherein a depth of the second trench structure is larger than a depth of the buried layer.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventor: Ching-Hung Kao