Patents by Inventor Ching-Yu Chen
Ching-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991479Abstract: The disclosure provides a time-lapse photographic device. The time-lapse photographic device includes a camera module, a drive module, an environment detection module, and a control unit. The drive module is connected to the camera module to drive the camera module to rotate. The environment detection module is configured to detect an external environment of the time-lapse photographic device to generate an environment detection signal. The control unit is electrically connected to the camera module, the drive module, and the environment detection module. The control unit generates, according to a shooting stop parameter, a plurality of intermittent drive signals to control the drive module, and controls the camera module to shoot at intervals of the drive signals. The control unit adjusts operation of at least one of the camera module and the drive module according to the environment detection signal.Type: GrantFiled: February 15, 2022Date of Patent: May 21, 2024Assignee: ASUSTEK COMPUTER INC.Inventors: Hsin-Yi Pu, Kai-Yu Hsu, Lai-Peng Wong, Chieh Li, Ting-Han Chang, Ching-Xsuan Chen
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Patent number: 11984316Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.Type: GrantFiled: May 22, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
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Publication number: 20240153842Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20240141553Abstract: A manufacturing process is described to evaluate and select raw semiconductor wafers in preparation for epitaxial layer formation. The manufacturing process first produces a single crystal ingot during which a seed pulling velocity and temperature gradient are closely controlled. The resulting ingot is vacancy-rich with relatively few self-interstitial defects. Selected wafers can advance to a high-temperature nitridation annealing operation that further reduces the number of interstitials while increasing the vacancies. Substrates characterized by a high vacancy density can then be used to optimize an epitaxial layer deposition process.Type: ApplicationFiled: March 28, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pu-Fang CHEN, Ching Yu Chen
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Patent number: 11972537Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.Type: GrantFiled: August 19, 2022Date of Patent: April 30, 2024Assignee: YU JUNG CHANG TECHNOLOGY CO., LTD.Inventors: Chih-Chuan Chen, Wei-Hsiang Tsai, Chin-Yu Chen, Ching-Cherng Sun, Jann-Long Chern, Yu-Kai Lin
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Publication number: 20240136184Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Ching-Yu Chang, Jei Ming Chen, Tze-Liang Lee
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Patent number: 11963969Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.Type: GrantFiled: September 16, 2022Date of Patent: April 23, 2024Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATIONInventors: Chia-Yu Chang, Shinn-Zong Lin, Hsiao-Chien Ting, Hui-I Yang, Horng-Jyh Harn, Hong-Lin Su, Ching-Ann Liu, Yu-Shuan Chen, Tzyy-Wen Chiou, Tsung-Jung Ho
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Patent number: 11964358Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.Type: GrantFiled: March 19, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
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Publication number: 20240130246Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
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Publication number: 20240130038Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.Type: ApplicationFiled: November 23, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Chin-Hsun WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Hung, Wei-Yu Liao, Chi-Min Chang
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Patent number: 11957061Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
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Publication number: 20240112905Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.Type: ApplicationFiled: November 30, 2023Publication date: April 4, 2024Inventors: Ching-Yu Chang, Jei Ming Chen, Tze-Liang Lee
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Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
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Patent number: 11948949Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.Type: GrantFiled: July 15, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
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Publication number: 20240105642Abstract: A method of manufacturing a package structure at least includes the following steps. An encapsulant laterally is formed to encapsulate the die and the plurality of through vias. A plurality of first connectors are formed to electrically connect to first surfaces of the plurality of through vias. A warpage control material is formed over the die, wherein the warpage control material is disposed to cover an entire surface of the die. A protection material is formed over the encapsulant and around the plurality of first connectors and the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.Type: ApplicationFiled: November 29, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
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Publication number: 20240106757Abstract: A method of wireless signal transmission management includes transmitting a plurality of data packets to tethering equipment from user equipment to tethering equipment, determining a size of each of the plurality of data packets by the tethering equipment, designating data packets of the plurality of data packets having a specific range of sizes as control signal packets by the tethering equipment, and prioritizing in transmitting the control signal packets to a cellular network by the tethering equipment.Type: ApplicationFiled: September 21, 2023Publication date: March 28, 2024Applicant: MEDIATEK INC.Inventors: Ching-Hao Lee, Yi-Lun Chen, Ho-Wen Pu, Yu-Yu Hung, Jun-Yi Li, Ting-Sheng Lo
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Patent number: 11942464Abstract: In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.Type: GrantFiled: July 19, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Jan Pei, Hsiu-Jen Lin, Wei-Yu Chen, Philip Yu-Shuan Chung, Chia-Shen Cheng, Kuei-Wei Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20240096498Abstract: A method for evaluating a risk of a subject getting a specific disease includes steps of: storing a reference database that contains original parameter sets; selecting target alleles from an SNP profile derived from genome sequencing data of a subject; selecting target parameter sets from among the original parameter sets; calculating, for each of the target parameter sets, a race factor based on a global risk allele frequency and a group-specific risk allele frequency included in the target parameter set; calculating a genetic factor based on statistics, global reference allele frequencies, the race factors for the target parameter sets, and numbers of chromosomes in homologous chromosome pairs included in the target parameter sets; calculating a citation factor based on numbers of citation times included in the target parameter sets; and calculating a risk score based on the genetic factor and the citation factor.Type: ApplicationFiled: August 28, 2023Publication date: March 21, 2024Inventors: Yi-Ting CHEN, Sing-Han HUANG, Ching-Yung LIN, Xiang-Yu LIN, Cheng-Tang WANG, Raksha NANDANAHOSUR RAMESH, Pei-Hsin CHEN
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Publication number: 20240096756Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Patent number: 11935757Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin