Patents by Inventor Chong Zhang

Chong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088052
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
  • Patent number: 11923312
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
  • Publication number: 20240073583
    Abstract: The present disclosure discloses an earphone. The earphone may include a hook-shaped component, a connecting component, and a holding component. When the earphone is in a wearing state, the hook-shaped component may be configured to hang between a rear side of an ear of a user and a head of the user. The holding component may be configured to contact a front side of the ear. The connecting component may be configured to connect the hook-shaped component and the holding component and extend from the head to an outside of the head to cooperate with the hook-shaped component to provide the holding component with a pressing force on the front side of the ear.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: SHENZHEN SHOKZ CO., LTD.
    Inventors: Zeying ZHENG, Jiang XU, Yonggen WANG, Haofeng ZHANG, Gan LAI, Chong WANG, Liwei WANG, Ruixin HAN, Lei ZHANG, Junjiang FU
  • Patent number: 11914203
    Abstract: A substrate includes a first area in which a laser array chip is disposed. The substrate includes a second area in which a planar lightwave circuit is disposed. The second area is elevated relative to the first area. A trench is formed in the substrate between the first area and the second area. The substrate includes a third area in which an optical fiber alignment device is disposed. The third area is located next to and at a lower elevation than the second area within the substrate. The planar lightwave circuit has optical inputs facing toward and aligned with respective optical outputs of the laser array chip. The planar lightwave circuit has optical outputs facing toward the third area. The optical fiber alignment device is configured to receive optical fibers such that optical cores of the optical fibers respectively align with the optical outputs of the planar lightwave circuit.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: February 27, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Michael Davenport, Mark Wade, Chong Zhang
  • Publication number: 20240059605
    Abstract: A low dielectric sealing glass powder for a miniature radio-frequency glass insulator is made of the following raw materials expressed in molar percentages: SiO2: 70.5-74.0%, B2O3: 20.5-23.5%, Ga2O3: 0.5-2.0%, P2O5: 0.25-2.0%, Li2O: 0.4-6.0%, K2O: 0.1-1.5%, LaB6: 0.05-1.0%, and NaCl: 0.03-0.3%. The raw material components are simple, and the preparation method is easy to implement. The dielectric constant and dielectric loss of the prepared glass powder are low, and the melting and molding temperature is low, which are convenient for large-scale industrial production. The melting and molding temperature of the low dielectric sealing glass powder ranges from 1320° C. to 1360° C., and the obtained glass has a dielectric constant ranging from 3.8 to 4.1 and a dielectric loss ranging from 4×10?4 to 10×10?4 at a frequency of 1 MHz, and a sealing temperature ranging from 900° C. to 950° C.
    Type: Application
    Filed: April 24, 2022
    Publication date: February 22, 2024
    Applicant: CNBM RESEARCH INSTITUTE FOR ADVANCED GLASS MATERIALS GROUP CO., LTD
    Inventors: Shou PENG, Chong ZHANG, Weiwei WANG, Changqing LI, Jinwei LI, Xiaofei YANG, Gang ZHOU, Zhenkun KE, Xin CAO, Chuanli SHAN, Jia NI, Jiedong CUI, Fengyang ZHAO, Zhaojin ZHONG, Pingping WANG, Qiang GAO, Na HAN, Lifen SHI, Yong YANG
  • Patent number: 11899251
    Abstract: A vertical integrated photonics chiplet assembly includes a package substrate and an external device connected to a top surface of the package substrate. A photonics chip is disposed within the package substrate. The photonics chip includes optical coupling devices positioned at a top surface of the photonics chip. A plurality of conductive via structures are disposed within the package substrate in electrical connection with electrical circuits within the photonics chip. The plurality of conductive via structures are electrically connected through the package substrate to the external device. An opening is formed through the top surface of the substrate to expose a portion of the top surface of the photonics chip at which the optical coupling devices are positioned. An optical fiber array is disposed and secured within the opening such that a plurality of optical fibers of the optical fiber array optically couple to the optical coupling devices.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 13, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Chong Zhang, Roy Edward Meade
  • Publication number: 20230418005
    Abstract: A first chip includes a first plurality of optical waveguides exposed at a facet of the first chip. A second chip includes a second plurality of optical waveguides exposed at a facet of the second chip. The second chip includes first and second spacers on opposite sides of the second plurality of optical waveguides. The first and second spacers have respective alignment surfaces oriented substantially parallel to the facet of the second chip at a controlled perpendicular distance away from the facet of the second chip. The second chip is positioned with the alignment surfaces of the first and second spacers contacting the facet of the first chip, and with the second plurality of optical waveguides respectively aligned with the first plurality of optical waveguides. The first and second spacers define and maintain an air gap of at least micrometer-level precision between the first and second pluralities of optical waveguides.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Inventors: Manan Raval, Matthew Sysak, Chen Li, Chong Zhang
  • Publication number: 20230420916
    Abstract: A device includes a first element having a passive waveguide structure supporting a first optical mode, a second element providing heat spreading functionality, a third element thermally coupled to the second element, having an active waveguide structure supporting a second optical mode, and a fourth element, at least partly butt-coupled to the third element, having an intermediate waveguide structure supporting intermediate optical modes. A tapered waveguide structure in either one of the first and fourth elements facilitates efficient adiabatic transformation between the first optical mode and one of the intermediate optical modes. No adiabatic transformation occurs between any of the intermediate optical modes and the second optical mode. Mutual alignments of the first, second, third and fourth elements are defined using lithographic alignment marks that facilitate precise alignment between layers formed during processing steps of fabricating the first, second, third and fourth elements.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Chong Zhang, Minh Tran, Tin Komljenovic
  • Publication number: 20230408767
    Abstract: A package assembly includes a photonic integrated circuit chip that includes an optical fiber attachment area. The package assembly also includes at least one optical fiber positioned within the optical fiber attachment area. The package assembly also includes a lid structure disposed over the at least one optical fiber. The package assembly also includes a plurality of soldered connections that secure the lid structure to the photonic integrated circuit chip. The plurality of soldered connections are configured to draw the lid structure toward the photonic integrated circuit chip so as to press the lid structure against the at least one optical fiber to mechanically hold the at least one optical fiber against the optical fiber attachment area. The package assembly also includes a package component to which the photonic integrated circuit chip is flip-chip attached after formation of the plurality of soldered connections.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 21, 2023
    Inventors: Derek M. Kita, Chong Zhang, John Fini, Li-Fan Yang
  • Publication number: 20230361534
    Abstract: A device comprises first, second, third and fourth elements fabricated on a common substrate. The first element comprises an active waveguide structure supporting a first optical mode, the second element comprises a passive waveguide structure supporting a second optical mode, the third element, at least partly butt-coupled to the first element, comprises an intermediate waveguide structure supporting intermediate optical modes, and a fourth element comprising TCO material that is attached to the first element. If the first optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation. No adiabatic transformation occurs between any of the intermediate optical modes and the first optical mode. Mutual alignments of the first, the second, the third, and the fourth elements are defined using lithographic alignment marks.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Applicant: Nexus Photonics, Inc.
    Inventors: Chong ZHANG, Minh TRAN, Tin KOMLJENOVIC
  • Patent number: 11808997
    Abstract: A device comprises first, second and third elements fabricated on a common substrate. The first element comprises an active waveguide structure comprising electrically pumped optical source supporting a first optical mode. The second element comprises a passive waveguide structure supporting a second optical mode in at least part of the second element. The third element, at least partly butt-coupled to the first element, comprises an intermediate waveguide structure supporting intermediate optical modes. At least part of the second element supports at least one optical mode that interacts with rare-earth dopants. A tapered waveguide structure in at least one of the second and the third elements facilitates efficient adiabatic transformation between the second optical mode and at least one of the intermediate optical modes. No adiabatic transformation occurs between any of the intermediate optical modes and the first optical mode.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: November 7, 2023
    Assignee: Nexus Photonics Inc.
    Inventors: Minh Tran, Tin Komljenovic, Chong Zhang
  • Publication number: 20230349720
    Abstract: A method for synchronizing neighboring tiles in an electronic map is described. The method includes grouping neighboring tiles of the electronic map into a plurality of tile groups. The method also includes selecting a first tile group and a second tile group that border one another on at least a first tile in the first tile group and a second tile in the second tile group. The method further includes independently optimizing the first tile group and the second tile group if a feature crosses between the first tile group and the second tile group. The method also includes shifting a border of the first tile group and a border of the second tile group to join the first tile and the second tile in the second tile group or the first tile group.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Applicants: TOYOTA RESEARCH INSTITUTE, INC., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hai JIN, Federico BONIARDI, Xipeng WANG, Paul OZOG, Chong ZHANG
  • Publication number: 20230352908
    Abstract: A device comprises first, second and third elements fabricated on a common substrate. The first element comprises an active waveguide structure supporting a first optical mode and at least one of the modal gain control structures. The second element comprises a passive waveguide structure supporting a second optical mode. The third element, at least partly butt-coupled to the first element, comprises an intermediate waveguide structure supporting intermediate optical modes. If the first optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in at least one of the second and third elements facilitate efficient adiabatic transformation between the second optical mode and one of the intermediate optical modes. No adiabatic transformation occurs between any of the intermediate optical modes and the first optical mode. Mutual alignments of the first, second and third elements are defined using lithographic alignment marks.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: Nexus Photonics, Inc.
    Inventors: Tin KOMLJENOVIC, Chong ZHANG, Minh TRAN
  • Publication number: 20230352385
    Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.
    Type: Application
    Filed: May 8, 2023
    Publication date: November 2, 2023
    Applicant: Tahoe Research, Ltd.
    Inventors: Yikang DENG, Ying WANG, Cheng XU, Chong ZHANG, Junnan ZHAO
  • Publication number: 20230294143
    Abstract: Provided are a laser cavitation composite ultrasonic cleaning device and cleaning method for a connecting rod, which belong to the technical field of bushing gap cleaning of engine connecting rods. Provided are a laser cavitation composite ultrasonic cleaning device and cleaning method for a connecting rod, the cleaning device comprises a cleaning tank, a bracket, a low-frequency ultrasonic vibrator, a first laser head, and a second laser head; the low-frequency ultrasonic vibrator is located on an outer side of a bottom portion of the cleaning tank; the first laser head is located above the bracket, and the second laser head is located at a lower portion in the cleaning tank. According to the cleaning device, laser light is combined with an ultrasonic wave, cooperated with light path assemblies, and the laser light is focused in a bolt hole and a bushing gap of the connecting rod.
    Type: Application
    Filed: August 1, 2022
    Publication date: September 21, 2023
    Inventors: Guan WANG, Junxian LI, Sihao LIN, Jieyu ZHU, Guohua CHEN, Chong ZHANG
  • Publication number: 20230300912
    Abstract: A session update method, which is applied to a terminal, includes: after a protocol data unit (PDU) session is established, receiving an indication message sent by a network-side device. The indication message includes a slice identifier, and the indication message is used for instructing a terminal to modify and re-establish the PDU session according to the slice identifier, or initiate a PDU session establishment flow.
    Type: Application
    Filed: August 11, 2021
    Publication date: September 21, 2023
    Applicants: CHINA MOBILE COMMUNICATION CO., LTD RESEARCH INSTITUTE, CHINA MOBILE COMMUNICATIONS GROUP CO., LTD.
    Inventors: Xu CHEN, Zhenning HUANG, Chong ZHANG, Yue SONG
  • Patent number: 11762154
    Abstract: A first chip includes a first plurality of optical waveguides exposed at a facet of the first chip. A second chip includes a second plurality of optical waveguides exposed at a facet of the second chip. The second chip includes first and second spacers on opposite sides of the second plurality of optical waveguides. The first and second spacers have respective alignment surfaces oriented substantially parallel to the facet of the second chip at a controlled perpendicular distance away from the facet of the second chip. The second chip is positioned with the alignment surfaces of the first and second spacers contacting the facet of the first chip, and with the second plurality of optical waveguides respectively aligned with the first plurality of optical waveguides. The first and second spacers define and maintain an air gap of at least micrometer-level precision between the first and second pluralities of optical waveguides.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Ayar Labs, Inc.
    Inventors: Manan Raval, Matthew Sysak, Chen Li, Chong Zhang
  • Publication number: 20230290043
    Abstract: Disclosed are a picture generation method performed by a computer device. The method includes: rendering a three-dimensional virtual scene to obtain a scene background rendering map; rendering a first foreground target reported by a first terminal associated with a first client to obtain a first foreground target rendering map; blending the scene background rendering map and the first foreground target rendering map to obtain a first picture, the first picture including the first foreground target displayed in the three-dimensional virtual scene; and providing the first picture to the first terminal associated with the first client for displaying the first picture. A technology of thousand people with thousand faces is achieved, the rendering efficiency can be improved, and the cost is saved.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Inventors: Wensheng CAO, Wei Cao, Tangxi Chen, Xiaojie Wang, Lijun Yuan, Chong Zhang, Meng Zhai, Xingyuan Zhu
  • Publication number: 20230280441
    Abstract: Disclosed are a position locking method of an underwater equipment, a terminal device, a system and a medium. The method comprises: acquiring an optical image and a sonar image taken by an underwater equipment; obtaining a target image by synthesizing the optical image and the sonar image, the target image including at least a target object; determining position offset information of the target object according to the target image; and generating position control parameters of the underwater equipment according to the position offset information, and sending position control parameters to the underwater equipment to make the underwater equipment to lock a position according to the position control parameters. The present application greatly reduces operation difficulty of the underwater equipment in turbid or undercurrent water areas.
    Type: Application
    Filed: August 17, 2022
    Publication date: September 7, 2023
    Applicant: SHENZHEN QYSEA TECH CO.,LTD
    Inventors: Wei SUN, ChoJu CHUNG, Chong ZHANG
  • Publication number: 20230266532
    Abstract: A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Inventors: Chong Zhang, Minh Tran, Tin Komljenovic, Hyun Dai Park