Abstract: An image processing method includes: acquiring an image size of an image and original image data of the image; creating a first texture storage area according to the image size, and storing image data of the image into the first texture storage area; creating, according to the image size and a target encoding format, a second texture storage area for storing target image data to be generated, a color encoding format corresponding to the target image data being the target encoding format; and performing, through a shader called by a graphics processor (GPU), encoding format conversion on the original image data stored in the first texture storage area to generate the target image data corresponding to each texture coordinate in the second texture storage area, and storing the target image data corresponding into the each texture coordinate to a corresponding storage location in the second texture storage area.

Abstract: A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Abstract: An interactive method and apparatus based on a virtual scene includes: receiving a virtual scene displaying operation; collecting a first scene image through a first camera coupled to a first terminal; and displaying a virtual environment picture, wherein the virtual environment picture includes a virtual scene and a matting object, the matting object copies a movement of a first object cutout from the first scene image and a movement of a second object cutout from a second scene image, where the second scene image is an image collected by a second camera coupled to a second terminal.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.

Abstract: The present invention belongs to the field of biotechnology, in particular to a multivalent fusion protein AB-NAC-189, method for producing the same, and uses thereof. The protein AB-NAC-189 is a fusion of a polypeptide segment AB, nascent polypeptide-associated complex (NAC), and a protein 189 corresponding to amino acids 1-189 from the N-terminal of protein HarpinEa. The fusion has the properties of a multivalent plant immune protein, thus it can effectively stimulate the hypersensitive response of tobacco leaves and has good thermal stability. While stimulating the immune response of plants, it can also improve the disease resistance of plants and promote plant growth. The AB-NAC-189 multivalent vaccine shows higher activity per unit concentration, and greater ability to promote growth of wheat and tobacco; meanwhile it can significantly promote chlorophyll synthesis in Goji berry, thereby improving the yield and quality of Goji berries.

Abstract: The present invention relates to a high-generation TFT-LCD glass substrate production line. The production line includes a kiln, a large-flow precious metal channel, a tin bath, an annealing kiln, a cutting machine and an unloading machine connected in sequence. The present invention combines high-efficiency melting, clarification and homogenization of molten glass, ultrathin float forming and annealing process technologies of the TFT-LCD glass, which can produce the TFT-LCD glass substrates with large sizes such as 8.5 generations and 10.5/11 generations, which has the advantages of large product size, excellent product performance, coherent process procedures, high production efficiency, high productivity and the like.

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to packages that include one or more glass cores that have thin film capacitors on one or more sides of the one or more glass cores. The film capacitors may be formed in-situ on the glass cores during substrate manufacturing. Other embodiments may be described and/or claimed.

Abstract: Embodiments may relate to a semiconductor package that includes a die and a glass core coupled with the die. The glass core may include a cavity with an interconnect structure therein. The interconnect structure may include pads on a first side that are coupled with the die, and pads on a second side opposite the first side. Other embodiments may be described and/or claimed.

Abstract: A sealing device and underwater machinery equipment are provided. The sealing device includes a sealing plug and a fixing assembly, wherein the sealing plug is in fixed connection with multiple cables, and the fixing assembly is constructed to fix the sealing plug on a sealed cabin in an abutting manner, such that the sealing plug is occluded in the sealed cabin. The underwater machinery equipment includes the sealing device as described above.

Abstract: A waterproof sealing structure for a cable and a communication device are provided. The waterproof sealing structure includes: a cable inner core, a cable sheath, fastening structures, and an actuating mechanism, wherein the cable sheath is molded by one-time pouring outside the cable inner core, the cable sheath comprises an elongated sheath and disc-shaped sheaths, the disc-shaped sheaths are molded at end portions of the elongated sheath, the end portions of the cable inner core are connected to the actuating mechanism, ends of the actuating mechanism connected to the cable inner core are open, and the disc-shaped sheaths are sealed and fastened at the open ends of the actuating mechanism through the fastening structures.

Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.

Abstract: Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.

Abstract: A multi-chip package assembly includes a substrate, a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. An optical fiber assembly including the plurality of optical fibers is positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector located at a distal end of the optical fiber assembly.

Abstract: The present invention belongs to the field of biotechnology, in particular to a multivalent fusion protein AB-NAC-189, method for producing the same, and uses thereof. The protein AB-NAC-189 is a fusion of a polypeptide segment AB, nascent polypeptide-associated complex (NAC), and a protein 189 corresponding to amino acids 1-189 from the N-terminal of protein HarpinEa. The fusion has the properties of a multivalent plant immune protein, thus it can effectively stimulate the hypersensitive response of tobacco leaves and has good thermal stability. While stimulating the immune response of plants, it can also improve the disease resistance of plants and promote plant growth. The AB-NAC-189 multivalent vaccine shows higher activity per unit concentration, and greater ability to promote growth of wheat and tobacco; meanwhile it can significantly promote chlorophyll synthesis in Goji berry, thereby improving the yield and quality of Goji berries.

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

Abstract: A large-flow precious metal channel is provided, which comprises a molten glass mixed-flow stirring section, at least two molten glass heating, clarifying and cooling sections are connected in parallel at one end of the molten glass mixed-flow stirring section, the other end of which is communicated with a liquid supply tank. The channel is mainly used for the clarification and homogenization of large-flow high-temperature molten glass in the production process of 8.5-generation and higher-generation TFT glass, and provides bubble-free and streak-free high-quality molten glass for subsequent float forming or overflow forming processes.