Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication and accumulation (MAC) operators. The plurality of memory banks include a plurality of even memory banks and a plurality of odd memory banks. The plurality of MAC operators include a first MAC operator configured to be shared by a first even memory bank among the plurality of even memory banks and a first odd memory bank among the plurality of odd memory banks. The first MAC operator is configured to alternately perform an even MAC operation and an odd MAC operation.

Abstract: A semiconductor device includes an information update control circuit configured to generate a self-read pulse for a self-read operation, a self-write pulse for a self-write operation, and an information update section signal that is activated during an information update section when an active operation is performed, and a column control circuit configured to receive the self-read pulse and the self-write pulse, to generate a read column strobe pulse for outputting data or selection information data stored in a core circuit when the self-read operation is performed based on the self-read pulse or the read operation is performed according to the read pulse, and to generate a write column strobe pulse for storing the data or the selection information data in the core circuit when the self-write operation is performed based on the self-write pulse or the write operation is performed according to the write pulse.

Abstract: A processing-in-memory (PIM) device includes a processing-in-memory (PIM) device includes a memory bank including a left memory bank and a right memory bank, a first global buffer, a second global buffer, a left multiplying-and-accumulating (MAC) operator configured to perform a MAC operation on a first set of a plurality of weight data and a first set of a plurality of vector data, a right MAC operator configured to perform the MAC operation on a second set of the plurality of the weight data and a second set of the plurality of the vector data, and a bias data converter configured to receive bias input data and output bias output data, wherein the bias output data includes a range of numbers that is increased over a range of numbers of the bias input data and includes a value equal to half the value of the bias input data.

Abstract: A processing-in-memory (PIM) system includes a host including an identification (ID)-channel mapper configured to generate a channel address corresponding to an identification received from outside the PIM system, and a plurality of PIM controllers coupled to the host through a plurality of channels, and the plurality of PIM devices coupled to the plurality of PIM controllers through the plurality of channels.

Abstract: A shift array circuit generates output data having the number of bits greater than the number of bits of target data by shifting the target data by a bit corresponding to a value of shift data. The shift array circuit includes a plurality of shift arrays. The plurality of shift arrays is configured to receive bits of the shift data for each bit and each configured to perform a shift operation on input data that is input to each of the plurality of shift arrays by a shift bit corresponding to an input bit, among the bits of the shift data.

Abstract: A semiconductor device includes a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal. The semiconductor device also includes a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells based on the internal clock and the internal control signal. The semiconductor device further includes a data control circuit configured to output data stored in the first memory cells based on the test command, and to store data output from the first memory cells in the second memory cells.

Abstract: An arithmetic device includes a function storage circuit and an activation function (AF) circuit. The function storage circuit stores and outputs a function selection signal, a first function information signal, and a second function information signal. The AF circuit generates an activation function result data by applying a slope value and a maximum value to a multiplication/accumulation (MAC) result data in a function setting mode that is activated by the function selection signal. The slope value is set based on the first function information signal, and the maximum value is set based on the second function information signal.

Abstract: An arithmetic device includes an activation function (AF) control circuit and a data storage circuit. The AF control circuit is configured to generate an activation period signal, an activation active signal, and an activation read signal based on an activation control signal. The data storage circuit includes at least one memory bank that is activated based on a bank active signal that is generated based on the activation active signal. The data storage circuit is configured to output data stored in a memory cell array, which is selected by a row address and a column address, as activation data based on the activation read signal.

Abstract: An electronic device includes an error correction circuit configured to detect an error included in internal data, to generate a failure detection signal during a read operation, and to correct the error included in the internal data during a refresh operation, and a core circuit configured to store an address signal for activating a word line in which the internal data including the error is stored through as a failure address signal when the failure detection signal is input to the core circuit, and store the error-corrected internal data in the core circuit through a word line activated by the failure address signal during the refresh operation.

Abstract: A semiconductor die stack includes a lower semiconductor die and an upper semiconductor die. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region. The second upper bonding pad and the first lower bonding pad are vertically aligned and directly bonded to each other. The second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

Abstract: An arithmetic device includes an AF circuit including a first table storage circuit. The AF circuit stores a table input signal into one variable latch selected based on an input selection signal among variable latches included in the first table storage circuit in a look-up table form when a table set signal is activated. The AF circuit extracts a result value of a first activation function realized by a look-up table based on an input distribution signal to output the extracted result value as a fist table output signal for generating an output distribution signal.

Abstract: A multiplication-accumulation (MAC) includes a multiplication circuit, a pre-processing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floating-point format to output a plurality of multiplication data. The pre-processing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of pre-processed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.

Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.

Abstract: A processing-in-memory (PIM) system includes a first and second PIM devices and a host. Each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators and a plurality of memory banks supplying weight data to the plurality of MAC operators. The host controls the first and second PIM devices and includes a data buffer. The first and second PIM devices include a first global buffer and a second global buffer, which supply the vector data to the plurality of MAC operators, respectively. The host reads the vector data out of the first and second PIM devices to store the vector data into the data buffer and writes the vector data stored in the data buffer into the first and second global buffers.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area. The memory controller is configured to control read operations of the memory device. The memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.

Abstract: A semiconductor device may include: a first substrate; a first high-frequency signal through electrode and a first low-frequency signal through electrode passing through the first substrate; a first high-frequency signal conductive pattern and a first low-frequency signal conductive pattern respectively connected to the first high-frequency signal through electrode and the first low-frequency signal through electrode; and one or more first high-frequency signal connection electrodes and one or more first low-frequency signal connection electrodes respectively connected to the first high-frequency signal conductive pattern and the first low-frequency signal conductive pattern, wherein an area of the first low-frequency signal conductive pattern is larger than an area of the first high-frequency signal conductive pattern.

Abstract: A semiconductor system includes a controller configured to generate a command and an address for performing a row hammering tracking operation and performing a precharge operation on a bank on which a tracking write operation of the row hammering tracking operation has been completed and a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to count an active number of the bank that is stored in the row hammering storage circuit by performing a tracking read operation of the row hammering tracking operation based on the command and the address, then store, in the row hammering circuit, the active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation, and perform the precharge operation on the bank based on the command.

Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.

Abstract: A processing-in-memory (PIM) device includes a data selection circuit, a multiplying-and-accumulating (MAC) circuit, and an accumulative adding circuit. The data selection circuit generates selection data from input data and zero-point data based on a zero-point selection signal. The MAC circuit performs a MAC arithmetic operation for the selection data to generate MAC result data. The accumulative adding circuit accumulatively adds MAC sign data based on a MAC output latch signal to generate MAC latch data. A sign of the MAC sign data is determined by the zero-point selection signal.