Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.

Abstract: A processing-in-memory (PIM) device includes a data selection circuit, a multiplying-and-accumulating (MAC) circuit, and an accumulative adding circuit. The data selection circuit generates selection data from input data and zero-point data based on a zero-point selection signal. The MAC circuit performs a MAC arithmetic operation for the selection data to generate MAC result data. The accumulative adding circuit accumulatively adds MAC sign data based on a MAC output latch signal to generate MAC latch data. A sign of the MAC sign data is determined by the zero-point selection signal.

Abstract: An arithmetic device includes an arithmetic circuit configured to perform an arithmetic operation to output arithmetic result data and a data output unit configured to feedback bias data to the arithmetic circuit prior to the arithmetic operation.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator and performing one operation, among a memory operation and a PIM operation, a command mapping register generating one of a memory operation mode signal and a PIM operation mode signal based on a row address that is mapped to the PIM operation to be performed by the plurality of MAC units, and a command decoder generating a memory control signal for the memory operation and a PIM control signal for the PIM operation, wherein the command decoder is configured to generate the PIM control signal in response to the PIM operation mode signal and configured to transmit the PIM control signal to the plurality of MAC units, and configured to generate the memory control signal in response to the memory operation mode signal and configured to transmit the memory control signal to the plurality of MAC units.

Abstract: A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Abstract: A semiconductor device includes a memory circuit including first and second banks and configured to count the numbers of inputs of first and second active signals for executing active operations on the first and second banks to generate a counting signal and to generate first and second hammering detection signals when the numbers of inputs of the first and second active signals are equal to or greater than a set number, and an active control circuit configured to store an active address as a target address when at least one of the first and second hammering detection signals is enabled, and to execute addition and subtraction operations on the target address to output a result of the addition and subtraction operations as an internal address for at least one of the first and second banks for executing a smart refresh operation, based on the counting signal in a refresh operation.

Abstract: A semiconductor system includes a controller configured to generate a command and an address for performing a row hammering tracking operation and performing a precharge operation on a bank on which a tracking write operation of the row hammering tracking operation has been completed and a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to count an active number of the bank that is stored in the row hammering storage circuit by performing a tracking read operation of the row hammering tracking operation based on the command and the address, then store, in the row hammering circuit, the active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation, and perform the precharge operation on the bank based on the command.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A neural network system includes a data type converter and a MAC operator. The data type converter may convert 32-bit floating-point format into one of a plurality of 16-bit floating-point formats. The MAC operator may perform MAC operations using 16-bit floating-point format data converted by the data type converter. The MAC operator includes a data type modulator configured to modulate the bit number of the converted 16-bit floating-point format to provide a modulated floating-point format with bit number different from the bit number of the converted 16-bit floating-point format.

Abstract: A processing-in-memory (PIM) controller includes a read/arithmetic queue logic circuit, a write queue logic circuit, and a scheduling logic circuit. The read/arithmetic queue logic circuit is configured to store a read queue and an arithmetic queue. The write queue logic circuit is configured to store a write queue for requesting to write data in the PIM device. The scheduling logic circuit is configured to perform the scheduling operation such that the write queue logic circuit outputs the arithmetic write queue before the read/arithmetic queue logic circuit outputs the arithmetic queue when the arithmetic queue exists in the read/arithmetic queue logic circuit and the arithmetic write queue exists in the write queue logic circuit.

Abstract: There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a zero-detection circuit and multiplier. The zero-detection circuit including first transfer gates, second transfer gates, and an output control logic circuit. The first controller and the second controller are configured to receive a first output value and a second output value generated by inverting the first output value. The first output value is having a value of “1” when all bits of the first data or the second data have a value of “0”. The output control logic circuit is configured to generate zero data including bits having a value of ‘0’ as output data of the multiplier when the second output value is a value of ‘0’.

Abstract: A memory system may include: a memory device including a plurality of memory cells; and a memory controller configured to store, as a fail address, a first internal address that is generated during a first read operation when at least one memory cell that is accessed during the first read operation among the plurality of memory cells is determined to be a fail, and store, as alternative data, internal read data that is generated during the first read operation.

Abstract: A Processing-In-Memory (PIM) device includes a first storage region and a multiplication/accumulation (MAC) calculator. The first storage region configured to store a first data. The MAC operator configured to execute a MAC calculation on the first data and second data in an MAC mode. When an error exists in the first data, the MAC operator compensates multiplication result data generated by a multiplying calculation of the first data and the second data and executes an adding calculation of the compensated multiplication result data.

Abstract: A processing-in-memory (PIM) controller includes a read/arithmetic queue logic circuit, a write queue logic circuit, and a scheduling logic circuit. The read/arithmetic queue logic circuit stores read queues and arithmetic queues, generates an arithmetic mode signal when an arithmetic queue exists in the read/arithmetic queue logic circuit, and outputs the arithmetic queue in response to an arithmetic mode enablement signal. The write queue logic circuit stores write queues, generates an arithmetic write signal when an arithmetic write queue exists in the write queue logic circuit, and outputs the write queue in response to an arithmetic write enablement signal. The scheduling logic circuit transmits the arithmetic mode enablement signal to the read/arithmetic queue logic circuit in response to the arithmetic mode signal and transmits the arithmetic write enablement signal to the write queue logic circuit in response to the arithmetic write signal.

Abstract: A normalizer includes a “0” search circuit configured to search for a position of a most significant “0” bit of first mantissa data included in input data to output first search data, a “1” search circuit configured to search for a position of a most significant “1” bit of the first mantissa data included in the input data to output second search data, a selector configured to output one selected by a bit value of first sign data of the input data between the first search data and the second search data, as selected data, an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data, and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the output data.

Abstract: A processing-in-memory (PIM) system includes a plurality of PIM devices, a plurality of PIM controllers configured to control respective ones of the plurality of PIM devices, and an interface coupled between a host and the plurality of PIM controllers. The interface transmits first request data to a target PIM controller corresponding to one of the plurality of PIM controllers for execution of a first request output from the host. The interface transmits second request data to all of the plurality of PIM controllers for execution of a second request output from the host.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.