Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area. The memory controller is configured to control read operations of the memory device. The memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.

Abstract: A processing-in-memory (PIM) device includes a first group of storage regions, a second group of storage regions, and a plurality of multiplication/accumulation (MAC) operators. The MAC operators are configured to communicate with the first and second groups of storage regions through a global data input/output (GIO) line. A first storage region corresponding to a storage region of the first group of storage regions, a second storage region corresponding to a storage region of the second group of storage regions, and a first MAC operator corresponding to a MAC operator of the plurality of MAC operators constitute a MAC unit. The first MAC operator is configured to receive first data and second data from the first and second storage regions, respectively, through the GIO line to perform a MAC arithmetic operation of the first and second data and to output a result of the MAC arithmetic operation.

Abstract: A semiconductor system includes a controller configured to, in a write operation, output write data and a write error code through at least any one of input/output lines, and in a read operation, receive read data and a read error code through at least any one of the input/output lines and detect a failure of the input/output lines depending on whether the read data is error-corrected; and a semiconductor device configured to, in the write operation, correct an error of the write data based on the write error code, store the error-corrected write data and store the write error code, and in the read operation, correct an error of the write data based on the write error code stored in the write operation, output the error-corrected write data as the read data, and output the write error code stored in the write operation, as the read error code.

Abstract: A processing-in-memory (PIM) system includes a host configured to generate a first request for a memory access operation and a second request for an arithmetic operation, a PIM controller configured to generate a first command based on the first request or the second request, a high speed interface configured to generate a second command based on the second request, and a PIM device configured to perform the memory access operation in response to the first command from the PIM controller and to perform the arithmetic operation in response to the second command from the high speed interface.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A multiplying-and-accumulating (MAC) circuit includes a multiplying circuit and an adding circuit. The multiplying circuit includes a first multiplier and a second multiplier, and each of the first multiplier and the second multiplier performs a multiplying calculation for first input data with N bits and second input data with M bits to output multiplication result data with (N+M) bits (where, “N” and “M” are natural numbers which are equal to or greater than one). The adding circuit includes an adder which performs an adding calculation for the multiplication result data of the first multiplier and the multiplication result data of the second multiplier to output addition result data with (N+M) bits.

Abstract: A processing-in-memory (PIM) device includes a command decoder configured to repeatedly output internal multiplication and accumulation (MAC) operation control signals at a predetermined cycle in response to a MAC operation command received from outside the PIM device, a MAC unit configured to perform MAC operations in response to the internal MAC operation control signals, and an address signal generator configured to repeatedly transmit internal address signals designating storage positions of weight data and vector data that are used for the MAC operations to the MAC unit at the predetermined cycle, based on an address signal received from outside the PIM device.

Abstract: An arithmetic device includes an arithmetic circuit configured to perform an arithmetic operation to output arithmetic result data and a data output unit configured to feedback bias data to the arithmetic circuit prior to the arithmetic operation.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a zero-detection circuit and multiplier. The zero-detection circuit including first transfer gates, second transfer gates, and an output control logic circuit. The first controller and the second controller are configured to receive a first output value and a second output value generated by inverting the first output value. The first output value is having a value of “1” when all bits of the first data or the second data have a value of “0”. The output control logic circuit is configured to generate zero data including bits having a value of ‘0’ as output data of the multiplier when the second output value is a value of ‘0’.

Abstract: A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication/accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

Abstract: A multiple operation circuit includes a multiplier, an adder, a latch circuit, and a plurality of selectors. The multiplier performs a multiplying calculation of first input data and second input data to generate and output multiplication result data. The adder performs an adding calculation of third input data and fourth input data to generate and output addition result data. The latch circuit latches fifth input data input to an input terminal of the latch circuit to generate and output feedback data. The plurality of selectors change transmission paths of first result data, the first input data, the second input data, the multiplication result data, and the addition result data according to a first operation mode, a second operation mode, or a third operation mode.

Abstract: A multiplication and accumulation (multiplication/accumulation) (MAC) operator includes a plurality of multiple operation circuits. The plural sets of first input data are transmitted to the plurality of multiple operation circuits, respectively. The plural sets of second input data are transmitted to the plurality of multiple operation circuits, respectively. The plural sets of operation result data are output from the plurality of multiple operation circuits, respectively. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

Abstract: A semiconductor device includes a core output driver, a pad input driver, and an arithmetic result data generation circuit. The core output driver transmits a first data, output from a core region, to a global input/output (I/O) line when an arithmetic operation is performed. The pad input driver transmits a second data, input through a pad region, to the global I/O line when the arithmetic operation is performed. The arithmetic result data generation circuit sequentially receives the first data and the second data through the global I/O line, to generate a core data and a pad data. The arithmetic result data generation circuit also performs an arithmetic operation, used in a neural network, based on the core data and the pad data, to generate arithmetic data.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A processing-in-memory (PIM) device includes a plurality of storage regions, a global buffer, and a plurality of multiplication/accumulation (MAC) circuits. The plurality of MAC circuits are configured to perform a MAC operation of first data from the plurality of storage regions and second data from the global buffer. Each of the plurality of MAC circuits is categorized as either an active MAC circuit or an inactive MAC circuit. The MAC operation includes a selective MAC operation which is selectively performed by the active MAC circuit.

Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication/accumulation (MAC) operators. The MAC operators perform MAC arithmetic operations using data output from the plurality of memory banks and input into the MAC operators. A page is allocated to have a first page size in the plurality of memory banks in a memory mode. The page is allocated to have a second page size, which is greater than the first page size, in the plurality of memory banks in a MAC arithmetic mode.

Abstract: A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.