Patents by Inventor Chris G. Martin
Chris G. Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8787101Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: August 5, 2013Date of Patent: July 22, 2014Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Publication number: 20130329510Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: ApplicationFiled: August 5, 2013Publication date: December 12, 2013Applicant: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Patent number: 8503258Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: September 14, 2012Date of Patent: August 6, 2013Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Publication number: 20130003473Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: ApplicationFiled: September 14, 2012Publication date: January 3, 2013Applicant: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Patent number: 8320206Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: November 15, 2010Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Patent number: 8054703Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.Type: GrantFiled: April 15, 2010Date of Patent: November 8, 2011Assignee: Round Rock Research, LLCInventor: Chris G. Martin
-
Publication number: 20110060888Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: ApplicationFiled: November 15, 2010Publication date: March 10, 2011Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Patent number: 7835207Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.Type: GrantFiled: October 7, 2008Date of Patent: November 16, 2010Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Patent number: 7813194Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.Type: GrantFiled: February 17, 2009Date of Patent: October 12, 2010Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Troy A. Manning, Brent Keeth
-
Publication number: 20100220537Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.Type: ApplicationFiled: April 15, 2010Publication date: September 2, 2010Applicant: ROUND ROCK RESEARCH, LLCInventor: Chris G. Martin
-
Patent number: 7715256Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.Type: GrantFiled: January 10, 2006Date of Patent: May 11, 2010Assignee: Round Rock Research, LLCInventor: Chris G. Martin
-
Publication number: 20100085825Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.Type: ApplicationFiled: October 7, 2008Publication date: April 8, 2010Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
-
Publication number: 20090147600Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.Type: ApplicationFiled: February 17, 2009Publication date: June 11, 2009Applicant: Micron Technology, Inc.Inventors: Chris G. Martin, Troy A. Manning, Brent Keeth
-
Patent number: 7492652Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.Type: GrantFiled: October 22, 2007Date of Patent: February 17, 2009Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Troy A. Manning, Brent Keeth
-
Patent number: 7408825Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.Type: GrantFiled: March 7, 2007Date of Patent: August 5, 2008Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Troy A. Manning, Brent Keeth
-
Patent number: 7382667Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.Type: GrantFiled: January 10, 2006Date of Patent: June 3, 2008Assignee: Micron Technology, Inc.Inventor: Chris G. Martin
-
Patent number: 7215586Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.Type: GrantFiled: June 29, 2005Date of Patent: May 8, 2007Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Troy A. Manning, Brent Keeth
-
Patent number: 7200022Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.Type: GrantFiled: August 3, 2004Date of Patent: April 3, 2007Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Brent Keeth, Brian Johnson, Walter L. Moden
-
Patent number: 7187601Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.Type: GrantFiled: November 29, 2004Date of Patent: March 6, 2007Assignee: Micron Technology, Inc.Inventor: Chris G. Martin
-
Patent number: 7160795Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.Type: GrantFiled: November 12, 2002Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Michael D. Chaine, Brent Keeth, Salman Akram, Troy A. Manning, Brian Johnson, Chris G. Martin, Todd A. Merritt, Eric J. Smith