Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract: A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A data capture circuit for an integrated circuit is disclosed which includes providing respective data paths between a latch and clock terminal and a latch and an associated data terminal, the length of each of the paths for a given latch device being approximately equal.

Abstract: A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally from a single edge of the lead frame. The lead fingers of each layer may extend in substantially the same direction. The electrically conductive buses of the two or more lead frame layers are at least partially superimposed with respect to one another. An insulator element is disposed between at least portions of the superimposed regions of the buses. One of the buses is connectable to a power supply source (VCC), while the other is connectable to a power supply ground (VSS). Thus, the mutually superimposed regions of the buses form a decoupling capacitor. Lead fingers of one of the layers may be arranged in groups which flank the remainder of the lead fingers so that they are not interleaved therewith.

Abstract: A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (Vcc), while the other is connectable to a power supply ground (Vss). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor.

Abstract: A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (Vcc), while the other is connectable to a power supply ground (Vss). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor.

Abstract: The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

Abstract: A technique for shifting the phase of a periodic signal. A periodic signal, such as a clock signal, may be provided in a synchronous system, such as a memory system implementing a Synchronous Dynamic Random Access Memory (SDRAM) device. It may be advantageous to be able to phase shift the signal. The present technique implements a delay line which includes a plurality of delay elements coupled in series. The periodic signal is delivered to the delay line and the time between transitions from high to low or low to high is stored in one of a number of latches coupled to the delay line at various points. A number of tapping elements are also coupled to the delay line at some incremental point corresponding to a correlative latch. By varying the proximity of each tapping element and corresponding latch along the delay line, various phase shifts of the periodic signal can be produced.