Patents by Inventor Chun-Cheng Lin
Chun-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11456226Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.Type: GrantFiled: April 27, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
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Patent number: 11424213Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.Type: GrantFiled: September 10, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Patent number: 11322421Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.Type: GrantFiled: July 9, 2020Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Publication number: 20220077102Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Publication number: 20220013422Abstract: Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Publication number: 20210373003Abstract: An irreversible and covalent method for immobilizing a glycoprotein includes the following steps. An organic boronic acid and a photoaffinity reagent are provided to contact a surface of a solid support, where the organic boronic acid is represented by R1—ArB(OH)2, —ArB(OH)2 is a boronic acid group, and R1 is a first cross-linking agent. The organic boronic acid is bound to the surface through the first cross-linking agent, and the photoaffinity reagent is bound to the surface through a second cross-linking agent R2. Next, a glycoprotein is provided to contact the organic boronic acid, and the glycoprotein includes an Fc fragment. An alcohol group on a sugar chain of the Fc fragment and the boronic acid group of the organic boronic acid form an organic boronate ester to immobilize the glycoprotein. UV light irradiation is then performed, so that the photoaffinity reagent and the glycoprotein form a covalent cross-link.Type: ApplicationFiled: July 7, 2020Publication date: December 2, 2021Applicant: National Tsing Hua UniversityInventors: Chun-Cheng Lin, Chen-Yu Fan, Yu-Ju Chen
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Patent number: 11163343Abstract: Systems and methods for a flexible Power Supply Unit (PSU) bay are described. In some embodiments, a chassis may include a surface and a PSU adaptor disposed on the surface, the PSU adaptor comprising a tab having a stopper coupled thereto, where the stopper is configured to: (a) resist movement, bending, or deformation of a board perpendicularly disposed with respect to the surface upon insertion of a first PSU into a PSU cage, and (b) move downward upon insertion of a second PSU into the PSU cage.Type: GrantFiled: September 4, 2020Date of Patent: November 2, 2021Assignee: Dell Products, L.P.Inventors: Chun-Cheng Lin, Yu-Lin Chen, Yueh-Chun Tsai, Jen-Chun Hsueh
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Patent number: 11158605Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.Type: GrantFiled: October 23, 2017Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
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Publication number: 20210020581Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
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Patent number: 10879192Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.Type: GrantFiled: July 17, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
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Patent number: 10832999Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.Type: GrantFiled: December 26, 2019Date of Patent: November 10, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Wei Huang, Wei-Hung Lin, Chih-Wei Lin, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20200258801Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.Type: ApplicationFiled: April 27, 2020Publication date: August 13, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
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Patent number: 10721835Abstract: An information handling system includes a bracket in physical contact with a server compute module. The bracket includes an adjustable guide that can rotate between a first position and a second position within the bracket. The adjustable guide is in the first position in response to a first peripheral card being inserted within the bracket, and is in the second position in response to a second peripheral card being inserted within the bracket.Type: GrantFiled: September 25, 2017Date of Patent: July 21, 2020Assignee: Dell Products, L.P.Inventors: Yu-LIn Chen, Chun-Cheng Lin, Kuang-Jye Tuan
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Publication number: 20200144171Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.Type: ApplicationFiled: December 26, 2019Publication date: May 7, 2020Inventors: Kuei-Wei Huang, Wei-Hung Lin, Chih-Wei Lin, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 10636715Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.Type: GrantFiled: January 19, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
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Publication number: 20200080942Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).Type: ApplicationFiled: March 16, 2018Publication date: March 12, 2020Applicant: iXensor CO., LTD.Inventors: Yenyu CHEN, An Cheng CHANG, Tai I CHEN, Su Tung YANG, Chih Jung HSU, Chun Cheng LIN, Min Han WANG, Shih Hao CHIU
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Patent number: 10522452Abstract: Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.Type: GrantFiled: October 18, 2011Date of Patent: December 31, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Wei Huang, Wei-Hung Lin, Chih-Wei Lin, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng, Ching-Shi Liu
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Publication number: 20190139845Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.Type: ApplicationFiled: January 19, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
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Publication number: 20190098789Abstract: An information handling system includes a bracket in physical contact with a server compute module. The bracket includes an adjustable guide that can rotate between a first position and a second position within the bracket. The adjustable guide is in the first position in response to a first peripheral card being inserted within the bracket, and is in the second position in response to a second peripheral card being inserted within the bracket.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Yu-Lin Chen, Chun-Cheng Lin, Kuang-Jye Tuan
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Patent number: 10215439Abstract: An information handling system includes first processing resources, e.g., GPGPU expansion cards, in a first thermal region of the system and second processing resources, e.g., one or more CPUs, in a second thermal region. The system may be configured to perform operations including determining a loading profile of the system. The loading profile indicates power consumption information for each of the thermal regions. One or more thermal fans may be configured in accordance with a fan configuration associated with the loading profile. The fan configuration defines a fan speed and airflow direction for one or more thermal fans and determines, in accordance with the fan speed and airflow direction of each thermal fan, a rotational angle of one or more rotatable airflow guides. The rotational angle of a rotatable airflow guide influences thermal fan airflow provided to one or more of the thermal regions.Type: GrantFiled: June 9, 2017Date of Patent: February 26, 2019Assignee: Dell Products L.P.Inventors: Chun-Cheng Lin, Yenlin Wang, Chih Min Su, Chun Chin Wen, Hsiang Jung Chin