Abstract: An information handling system includes first processing resources, e.g., GPGPU expansion cards, in a first thermal region of the system and second processing resources, e.g., one or more CPUs, in a second thermal region. The system may be configured to perform operations including determining a loading profile of the system. The loading profile indicates power consumption information for each of the thermal regions. One or more thermal fans may be configured in accordance with a fan configuration associated with the loading profile. The fan configuration defines a fan speed and airflow direction for one or more thermal fans and determines, in accordance with the fan speed and airflow direction of each thermal fan, a rotational angle of one or more rotatable airflow guides. The rotational angle of a rotatable airflow guide influences thermal fan airflow provided to one or more of the thermal regions.

Abstract: An information handling includes a plunger that secures a server planar board within the information handling system. The plunger includes a nut, a body, a rod, and a cap. The nut tightens toward the body and holds the server planar board between the nut and the body. The rod securely holds the server planar board within the information handling system in response to the plunger being in a locked position, and enables the server planar board to be removed from within the information handling system in response to the plunger being in an unlocked position. The cap includes a handle to provide a surface for a force to be exerted to cause the plunger to move from the locked position to the unlocked position.

Abstract: A heat exchanger includes first, second, and third heat sinks, multiple heat pipes located within the heat sinks, and a first aluminum bar located within the heat sinks. The first aluminum bar extends from an outside edge of the first heat sink, through the first, second, and third heat sinks, and to an outside edge of the third heat sink.

Abstract: An information handling system includes first processing resources, e.g., GPGPU expansion cards, in a first thermal region of the system and second processing resources, e.g., one or more CPUs, in a second thermal region. The system may be configured to perform operations including determining a loading profile of the system. The loading profile indicates power consumption information for each of the thermal regions. One or more thermal fans may be configured in accordance with a fan configuration associated with the loading profile. The fan configuration defines a fan speed and airflow direction for one or more thermal fans and determines, in accordance with the fan speed and airflow direction of each thermal fan, a rotational angle of one or more rotatable airflow guides. The rotational angle of a rotatable airflow guide influences thermal fan airflow provided to one or more of the thermal regions.

Abstract: A fluorous compound, a method of preparing a fluorous tagged protein, and a method of immobilizing protein are provided. The fluorous compound is represented by Y-L-R, wherein Y is a fluorous group; L is a linker, and the linker includes a bivalent group having a sulfo group, a bivalent group having a carboxyl group, or a bivalent group of hydrophilic amino acid; and R is a functional group capable of bonding to protein.

Abstract: A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film.

Abstract: A heat exchanger includes first, second, and third heat sinks, multiple heat pipes located within the heat sinks, and a first aluminum bar located within the heat sinks. The first aluminum bar extends from an outside edge of the first heat sink, through the first, second, and third heat sinks, and to an outside edge of the third heat sink.

Abstract: A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

Abstract: A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 ?m.

Abstract: An example device in accordance with an aspect of the present disclosure includes a base housing, display housing, and locking mechanism. The base housing includes a keyboard, and the display housing is pivotably coupled to the base housing. The locking mechanism is to lock key movement of the keyboard based on the display housing being pivoted according to a first range. The locking mechanism is to unlock key movement based on the display housing being pivoted according to a second range.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process.

Abstract: A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect.

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.