Patents by Inventor Chun-Chieh Wang

Chun-Chieh Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352564
    Abstract: Some implementations described herein provide a nanostructure transistor including inner spacers between a gate structure and a source/drain region. The inner spacers, formed in cavities at end regions of sacrificial nanosheets during fabrication of the nanostructure transistor, include concave-regions that face the source/drain region. Formation techniques include forming the sacrificial nanosheets and inner spacers to include certain geometric and/or dimensional properties, such that a likelihood of defects and/or voids within the inner spacers and/or the gate structure are reduced.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Chun Chieh WANG, Yueh-Ching PAI
  • Publication number: 20230354554
    Abstract: A heat dissipation system suitable for a portable electronic device with two heat sources is provided. The heat dissipation system includes a fan, two heat dissipation fin sets, a gate, a first heat pipe, a second heat pipe, and a control unit. The fan is a centrifugal fan and has a main outlet and a sub outlet. The heat dissipation fin sets are disposed respectively at the main outlet and the sub outlet, and the gate is disposed at the sub outlet. The first heat pipe thermally contacts the heat sources and the heat dissipation fin set located at the main outlet. The second heat pipe thermally contacts one of the heat sources and the two heat dissipation fin sets. The control unit is electrically connected to the gate to drive the gate to open or close the sub outlet according to a load of the two heat sources.
    Type: Application
    Filed: April 25, 2023
    Publication date: November 2, 2023
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Tsung-Ting Chen, Jau-Han Ke, Chun-Chieh Wang, Chi-Tai Ho, Kuan-Lin Chen
  • Publication number: 20230343645
    Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on exposed top surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in the top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes the oxidized portion of the seed layer. A second etch process removes portions of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 26, 2023
    Inventors: Meng-Shan WU, Chih-Hsun HSU, Jiang LU, Shiyu YUE, Chun-chieh WANG, Annamalai LAKSHMANAN, Yixiong YANG
  • Publication number: 20230343643
    Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.
    Type: Application
    Filed: July 19, 2022
    Publication date: October 26, 2023
    Inventors: Chih-Hsun HSU, Shiyu YUE, Wei LEI, Yi XU, Jiang LU, Yu LEI, Ziye XIONG, Tsung-Han YANG, Zhimin QI, Aixi ZHANG, Jie ZHANG, Liqi WU, Rongjun WANG, Shihchung CHEN, Meng-Shan WU, Chun-Chieh WANG, Annamalai LAKSHMANAN, Yixiong YANG, Xianmin TANG
  • Publication number: 20230343644
    Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.
    Type: Application
    Filed: November 28, 2022
    Publication date: October 26, 2023
    Inventors: Chih-Hsun HSU, Shiyu YUE, Jiang LU, Rongjun WANG, Xianmin TANG, Zhenjiang CUI, Chi Hong CHING, Meng-Shan WU, Chun-chieh WANG, Wei LEI, Yu LEI
  • Publication number: 20230337391
    Abstract: Provided is a centrifugal heat dissipation fan including a housing and an impeller. The impeller is disposed in the housing. The impeller has a hub and multiple blades disposed surrounding the hub. Every two adjacent blades have different blade structures relative to the housing such that the blade structures pass by a fixed position of the housing and generate blade tones of varying frequencies when the impeller rotates.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 19, 2023
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Tsung-Ting Chen, Sheng-Yan Chen, Chun-Chieh Wang
  • Publication number: 20230318204
    Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Applicant: HTC Corporation
    Inventors: Cheng-Hung LIN, Szu-Po WANG, Chia-Te CHIEN, Chun-Chieh WANG, Kang-Ling LI, Chun-Hsien LEE, Yu-Chieh CHIU
  • Patent number: 11775034
    Abstract: A heat dissipation system of a portable electronic device is provided. The heat dissipation system includes a body and at least one fan. A heat source of the portable electronic device is disposed in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet, at least one flow outlet, and at least one spacing portion. The flow outlet faces toward the heat source, and the spacing portion surrounds the flow inlet and abuts against the body, so as to isolate the flow inlet and the heat source in two spaces independent of each other in the body.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 3, 2023
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Kuang-Hua Lin, Chun-Chieh Wang, Shu-Hao Kuo
  • Patent number: 11777212
    Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: October 3, 2023
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 11742404
    Abstract: In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, conductive layers are formed on the gate dielectric layer to fully fill the gate space, the gate dielectric layer and the conducive layers are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not includes tungsten, and the contact metal layer includes tungsten.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Chieh Wang, Yueh-Ching Pai
  • Publication number: 20230262924
    Abstract: A thermal module includes a fan and a fin assembly. The fan has an air outlet. The fin assembly has multiple fins, and is disposed to the air outlet of the fan. The fins are disposed side by side to form multiple flow channels. Each of the flow channels has a first inlet, at least one second inlet, and an outlet. In each of the flow channels, a gas flow generated by the fan flows into the flow channel from the first inlet and flows out of the flow channel from the outlet, and a gas flow outside the fin assembly is drawn by the gas flow in the flow channel to flow into the flow channel from the at least one second inlet.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 17, 2023
    Applicant: Acer Incorporated
    Inventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
  • Fan
    Patent number: 11719252
    Abstract: A fan adapted for being disposed in an electronic device is provided. The fan includes a hub and a plurality of metal blades respectively extending from the hub. Each of the metal blades has a root portion connected to the hub and an end portion away from the hub, and a mass of the end portion is greater than a mass of the root portion, such that the metal blade is elongated while the fan is rotated.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 8, 2023
    Assignee: Acer Incorporated
    Inventors: Yu-Ming Lin, Wen-Neng Liao, Cheng-Wen Hsieh, Chun-Chieh Wang, Han-Liang Huang, Sheng-Yan Chen, Tsung-Ting Chen
  • Patent number: 11670541
    Abstract: A first photoresist material is formed. The first photoresist material is exposed through a phase shift mask. The first photoresist material is developed to form a first photoresist layer, wherein the first photoresist layer comprises a plurality of first photoresist patterns and a plurality of first openings between the plurality of first photoresist patterns. A first conductive material is formed in the plurality of first openings. A second photoresist layer is formed over the first conductive material, wherein the second photoresist layer comprises at least one second opening. A second conductive material is formed in the at least one second opening. The first photoresist layer and the second photoresist layer are removed, to form a plurality of first conductive patterns and at least one second conductive pattern. A dielectric layer is formed, wherein the at least one second conductive pattern is disposed in the dielectric layer.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Hung-Jui Kuo, Jaw-Jung Shin, Ming-Tan Lee
  • Publication number: 20230141521
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yu LIN, Chi-Yu Chou, Hsien-Ming Lee, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai, Chi-Jen Yang, Tsung-Ta Tang, Yi-Ting Wang
  • Publication number: 20230116357
    Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Kuo-Jung Huang, Huai-Tei Yang
  • Publication number: 20230109135
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Inventors: Chun-Chieh WANG, Yu-Ting LIN, Yueh-Ching PAI, Shih-Chieh CHANG, Huai-Tei YANG
  • Publication number: 20230102878
    Abstract: A projector and a projection method are provided. The projector includes a control device, a projection optical engine, a distance sensing device, and an image capturing device. The projection optical engine projects a first projection image to a projection surface according to first image data. The distance sensing device senses multiple distance parameters of a projection area. The image capturing device captures the first projection image to obtain a first captured image. The control device performs a keystone correction operation and a leveling correction operation on the first image data. The projection optical engine projects a second projection image to the projection surface according to the corrected first image data. The control device obtains a second captured image including the second projection image through the image capturing device, and analyzes the second captured image to project current projection image size information in the second projection image.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 30, 2023
    Applicant: Coretronic Corporation
    Inventors: Chun-Chieh Wang, Fan-Chieh Chang
  • Publication number: 20230081739
    Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.
    Type: Application
    Filed: March 22, 2022
    Publication date: March 16, 2023
    Applicant: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 11587791
    Abstract: A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Kuo-Jung Huang, Yueh-Ching Pai, Huai-Tei Yang
  • Patent number: 11583248
    Abstract: An ultrasound image system is provided. The ultrasound image system includes an ultrasound probe and a processing circuit. The ultrasound probe includes a substrate, a first transducer array and a second transducer array. The first transducer array is fixed disposed on the substrate and configured to receive a first ultrasound signal The second transducer array is fixed disposed on the substrate and configured to receive a second ultrasound signal. Each of the first transducer array and the second transducer array includes a plurality of ultrasound transducer elements arranged along a first direction. The ultrasound transducer elements of the first transducer array are interleaved with the ultrasound transducer elements of the second transducer array. The processing circuit is coupled to the first transducer array and the second transducer array and is configured to generate an ultrasound image signal according to the first ultrasound signal and the second ultrasound signal.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: February 21, 2023
    Assignee: Qisda Corporation
    Inventors: Fu-Sheng Jiang, Chun-Chieh Wang