Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A heat dissipation system of portable electronic device includes a body, at least one fan and at least one spacing member. At least one heat source of the portable electronic device is arranged in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet located in the axial direction and at least one flow outlet located in the radial direction. The spacing member is disposed on at least one of the body or the fan to form a stratified air flow in the body along the axial direction. The stratified air flows into the fan through the flow inlet and out of the fan through the flow outlet respectively.

Abstract: A time signal generating circuit of a power converter and a control method thereof are provided. The time signal generating circuit includes a reference frequency generating circuit, an on-time circuit and a frequency tracking circuit. The reference frequency generating circuit provides a reference frequency signal. The on-time circuit provides an on-time signal according to a first reference signal and a second reference signal. The second reference signal is related to an output voltage of the power converter. The frequency tracking circuit is coupled to the reference frequency generating circuit and the on-time circuit, and compares frequencies of the reference frequency signal and the on-time signal within a default time to generate a tracking signal. The on-time circuit adjusts the second reference signal according to the tracking signal, so that the on-time circuit adjusts the frequency of the on-time signal.

Abstract: A heat dissipation device includes a heat dissipation member and a fan. The heat dissipation member includes a first heat dissipation fin group and a second heat dissipation fin group stacked on the first heat dissipation fin group. The first heat dissipation fin group includes a plurality of first heat dissipation fins, and the second heat dissipation fin group includes a plurality of second heat dissipation fins. The fan is stacked on the second heat dissipation fin group. The fan is configured to rotate around an axis. The first heat dissipation fins and the second heat dissipation fins are arranged around the axis.

Abstract: The disclosure provides a power conversion circuit with a multi-function pin and a multi-function setting method thereof. The multi-function pin is coupled to an external setting circuit. The power conversion circuit includes a first function circuit, a second function circuit, and a judging circuit. The first function circuit is coupled to the multi-function pin. The second function circuit is coupled to the multi-function pin. The judging circuit is coupled to the multi-function pin, the first function circuit, and the second function circuit. The judging circuit provides a setting current to the multi-function pin, so that the external setting circuit generates a voltage according to the setting current. The judging circuit judges the type of external setting circuit according to voltage so as to activate the first function circuit or the second function circuit accordingly.

Abstract: A communication device includes a display device, a first antenna element, a second antenna element, a third antenna element, and a fourth antenna element. The display device is surrounded by the first antenna element, the second antenna element, the third antenna element, and the fourth antenna element. Any adjacent two of the first antenna element, the second antenna element, the third antenna element, and the fourth antenna element have different polarization directions.

Abstract: A first photoresist material is formed. The first photoresist material is exposed through a phase shift mask. The first photoresist material is developed to form a first photoresist layer, wherein the first photoresist layer comprises a plurality of first photoresist patterns and a plurality of first openings between the plurality of first photoresist patterns. A first conductive material is formed in the plurality of first openings. A second photoresist layer is formed over the first conductive material, wherein the second photoresist layer comprises at least one second opening. A second conductive material is formed in the at least one second opening. The first photoresist layer and the second photoresist layer are removed, to form a plurality of first conductive patterns and at least one second conductive pattern. A dielectric layer is formed, wherein the at least one second conductive pattern is disposed in the dielectric layer.

Abstract: A heat dissipation fan suited for being assembled in an electronic device is provided. The heat dissipation fan includes a hub and a plurality of fan blades disposed at and surrounding the hub. The fan blade has ductility and flexibility, and any two fan blades next to each other are in different thickness.

Abstract: A portable electronic device including a body, a door, a carrier and at least one electronic module is provided. The door is movably mounted on the body. The carrier includes a first side and a second side opposite to each other, the first side is pivoted to the body, and the second side is movably pivoted to the door. The electronic module is disposed on the carrier. At least one opening is formed between the door and the body when the door moves away from the body, and the door drives the carrier to rotate relative to the body, such that the electronic module is tilted with respect to the body along with the movement of the door, and the electronic module is exposed to an external environment via the opening for heat dissipation.

Abstract: An integrated circuit device includes a semiconductor substrate; and a pad region over the semiconductor substrate. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer over the pad region. The integrated circuit device further includes a conductive pillar on the UBM layer, wherein the conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes a protection structure over the sidewall surface of the conductive pillar, wherein sidewalls of the UBM layer are substantially free of the protection structure, and the protection structure is a non-metal material.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A control circuit of a power converter is coupled to an output stage and controls it to convert an input voltage into an output voltage and generate an output current. The control circuit includes a ripple generation circuit, a synthesis circuit, an error amplifier, a comparator and a PWM circuit. The ripple generation circuit generates a ripple signal according to an input voltage, an output voltage and output current. The synthesis circuit receives the ripple signal and a first feedback signal related to output voltage to provide a second feedback signal. The error amplifier receives the second feedback signal and a reference voltage to generate an error signal. The comparator receives a ramp signal and error signal to generate a comparison signal. The PWM circuit generates a PWM signal to control output stage according to the comparison signal. A slope of ripple signal is changed with the output current.

Abstract: A fan and a balance ring for the fan are provided. The fan includes a housing, a hub disposed in the housing, blades connected to the side surface of the hub, and a balance ring connected to the hub. The balance ring includes a ring chamber and a balance liquid filled in the ring chamber. The volume of the balance liquid is less than the volume of the ring chamber.

Abstract: Methods of manufacturing redistribution circuit structures are disclosed and one of the methods includes the following steps. A seed layer is formed over a die and an encapsulant encapsulating the die. A photoresist material is formed over the seed layer. The photoresist material is exposed through a phase shift mask to an I-line wavelength within an I-line stepper using a numerical aperture equal to or less than 0.18. The photoresist material is developed to form a photoresist layer including photoresist patterns and openings therebetween. A conductive material is formed in the openings. The photoresist patterns are removed to form conductive patterns. By using the conductive patterns as a mask, the seed layer is partially removed, to form seed layer patterns under the conductive patterns, wherein redistribution conductive patterns include the seed layer patterns and the conductive patterns respectively.

Abstract: A vapor chamber structure for heat dissipation of a heat source is provided. The vapor chamber structure includes a housing having a heat absorption side and a heat dissipation side, a first capillary structure disposed in the housing, and a working fluid filled in the housing. The first capillary structure is formed into cavities isolated from each other, and each of the cavities is connected between the heat absorption side and the heat dissipation side. Heat generated by the heat source is absorbed by the heat absorption side, thereby transforming the working fluid from liquid state to vapor state. The working fluid in the vapor state is transmitted to the heat dissipation side via the cavities, and is transformed to the liquid state while the heat is dissipated. The working fluid in the liquid state returns to the heat absorption side via the first capillary structure.

Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode, a gate dielectric layer is formed in the gate space, conductive layers are formed on the gate dielectric layer to fully fill the gate space, the gate dielectric layer and the conducive layers are recessed to form a recessed gate electrode, and a contact metal layer is formed on the recessed gate electrode. The recessed gate electrode does not includes tungsten, and the contact metal layer includes tungsten.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.