Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a first source pad, and a first drain pad. The source electrode, the drain electrode, and the gate electrode are disposed, on an active region of the active layer. The first insulating layer is disposed on the source electrode, the drain electrode, and the gate electrode. The first source pad and the first drain pad are disposed on the first insulating layer and the active region. The first source pad includes a first source body and a first source branch. The first source branch is electrically connected to the first source body and disposed on the source electrode. The first drain pad includes a first drain body and a first drain branch. The first drain branch is electrically connected to the first drain body and disposed on the drain electrode.

Abstract: A control method of speeding up light emission of a laser diode includes the following steps. First step is to boost the supply voltage from a first voltage potential to a second voltage potential before an emission period. At the beginning of the emission period, a current path conducts through the laser diode and a current source. One terminal of the laser diode is coupled to the current source, and the other terminal of the laser diode connects the supply voltage. When the current path is being conducted, the current source is in the transient state and provides a transient driving current; and the voltage difference between the two terminals of the laser diode is generated in response to the second voltage potential and is related to the transient driving current. When the transient driving current is larger than a threshold, the laser diode emits light.

Abstract: A plug connector includes a connector body defining a rear cable supporting platform with opposite first and second surfaces, a plurality of terminals and a cable. The terminal includes a pair of USB 2.0 signal soldering legs, a grounding and power soldering legs exposed to the first surface of the supporting platform and a detecting soldering leg, an additional power and grounding soldering legs exposed to the second surface. Wires of the cable consist of a pair of USB 2.0 signal wires, a power wire, a grounding wire welded with corresponding soldering legs on the first surface. The second surface of the supporting platform is further located with a SMT type resistor with a first leg and a second leg, the first leg is connected with the detecting soldering leg, the second leg is connected with the additional power soldering leg or the additional grounding soldering leg.

Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.

Abstract: A semiconductor device includes an element layer, plural source electrodes, plural drain electrodes, plural gate electrodes, a source bus bar, a drain bus bar, a first gate bus bar, and a second gate bus bar. The source electrodes, the drain electrodes, and the gate electrodes are disposed on the element layer and extend along a first direction. The gate electrodes are respectively disposed between the source and drain electrodes. The source and drain bus bars and the first and second gate bus bars extend along a second direction interlaced with the first direction. The source bus bar and the drain bus bar are electrically connected to the source electrodes and the drain electrodes, respectively. The first and second gate bus bars are connected to the gate electrodes. The first bus bar is disposed at one end of the source electrodes. The source electrode crosses the second gate bus bar.

Abstract: An electrical connector has a mating cavity opening forwardly. The electrical connector has a main body, a terminal module and a sealing member. The terminal module has an insulator and a plurality of conductive terminals received therein. The conductive terminals have contacting portions exposed into the mating cavity and connecting legs. The terminal module is received in the main body. The sealing member is filled in a gap between the terminal module and main body to seal the gap.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A receptacle connector includes an insulative housing defining a base and a mating tongue, with a widen and thicken step structure around a root thereof adjacent to the base; two rows of contacts disposed in the insulating housing with contacting sections exposed upon the mating tongue and mount tails out of the base; a metallic shield surrounding the mating tongue so as to define a mating cavity; and a metallic bracket attached the shield. The first wall of the shield defines a pair of spring tangs split therefrom and extending rearwards into the mating cavity, the second wall defines a pair of dimples protruding inwards the mating cavity for holding the plug connector. The bracket covers spring tangs and seals any opens defined on the first wall for keeping integrity therewith under EMI consideration.

Abstract: A plug connector includes a connector body defining a rear cable supporting platform with opposite first and second surfaces, a plurality of terminals and a cable. The terminal includes a pair of USB 2.0 signal soldering legs, a grounding and power soldering legs exposed to the first surface of the supporting platform and a detecting soldering leg, an additional power and grounding soldering legs exposed to the second surface. Wires of the cable consist of a pair of USB 2.0 signal wires, a power wire, a grounding wire welded with corresponding soldering legs on the first surface. The second surface of the supporting platform is further located with a SMT type resistor with a first leg and a second leg, the first leg is connected with the detecting soldering leg, the second leg is connected with the additional power soldering leg or the additional grounding soldering leg.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.

Abstract: A receptacle connector includes an insulative housing with a mating tongue, a plurality of contacts having front contacting sections exposed upon two opposite surfaces of the mating tongue and rear tail sections extending downwardly outside of the housing for mounting to a printed circuit board. A metallic shield encloses said housing and forms a capsular mating cavity with said mating tongue extending forwardly therein. A metallic shielding plate includes a front horizontal section embedded with the mating tongue to isolate the contacting sections of the contacts which are located on two different opposite surfaces, and a rear vertical section extending downwardly from a rear edge of the front horizontal section to isolate the tail sections of the contacts which are arranged in two rows with said rear vertical section therebewteen.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: A plug for provision of power includes a housing forming a receiving cavity with two opposite sites in a vertical direction which is compatible with a standard plug connector with twelve contacts on each site and a first and second rows of contacts on the sides while in diagonally symmetrical manner. Each contact includes a contacting section, and a connecting section for directly connecting to a corresponding wire. Each row of contacts is categorized with a pair of power contacts, a pair of grounding contacts and a specific contact without any high speed differential pair. Two pair of power contacts of both two rows are electrically connected together either via direct mechanical connection via vertical extensions or via indirect electrical connection via the latch which has a pair of side arms extending into the receiving cavity at two opposite transverse ends.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.