Patents by Inventor Chun-Hung Liao
Chun-Hung Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240156440Abstract: A method of reconstructing transcranial images using a dual-mode ultrasonic phased array includes steps of: controlling channels to emit energy toward an intracranial target point of a patient; respectively generating backscattered radiofrequency (RF) data by using the channels to receive backscattered energy reflected from the intracranial target; and reconstructing an acoustic distribution image based on those backscattered RF data in real-time. Compared with Pre-Treatment Ray Tracing Method, the present invention can display intracranial pressure distribution in real-time; compared with MR Thermometry, the present invention can be applied to low-energy applications without temperature change; and compared with Passive Cavitation Imaging, the present invention can stably present acoustic distribution images without relying on microbubbles.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Inventors: HAO-LI LIU, HSIANG-CHING LIN, ZHEN-YUAN LIAO, HSIANG-YANG MA, CHIH-HUNG TSAI, CHUN-HAO CHEN
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Publication number: 20240152187Abstract: A foldable electronic device including a first body, a second body, a hinge module, and a cover is provided. The hinge module is connected to the first body and the second body, such that the first body and the second body are rotated relatively to be folded or unfolded via the hinge module. The hinge module has a protruding rod eccentric to a rotation center of the hinge module. The cover is pivoted to the second body and located on a moving path of the protruding rod. The hinge module drives the cover to be rotated relative to the second body via the protruding rod.Type: ApplicationFiled: October 24, 2023Publication date: May 9, 2024Applicant: Acer IncorporatedInventors: Chun-Hung Wen, Chun-Hsien Chen, Hui-Ping Sun, Wen-Neng Liao, Yu-Ming Lin, Kuan-Lin Chen
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Patent number: 11978511Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.Type: GrantFiled: January 21, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
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Publication number: 20240145867Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.Type: ApplicationFiled: January 17, 2023Publication date: May 2, 2024Inventors: TE-CHAO LIAO, CHUN-CHE TSAO, CHENG-HUNG CHEN, LI-TING WANG
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Publication number: 20240136423Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.Type: ApplicationFiled: December 25, 2023Publication date: April 25, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11966107Abstract: An anti-peep display device includes a display module and an anti-peep module disposed on the display module. The anti-peep module includes the following features. The first light incident surface faces the display surface, the second and third light incident surfaces are located on opposite sides of the first light incident surface, the first condensing portion is disposed corresponding to the second light incident surface and the first light source, the second condensing portion is disposed corresponding to the third light incident surface and the second light source, the first and second condensing portions convert beams of the first and second light sources into anti-peep beams with a beam angle less than 10 degrees, and the optical microstructures reflect the anti-peep beams and exit the anti-peep beams from the light guide plate. The present invention also provides an anti-peep method applicable to the anti-peep display device.Type: GrantFiled: June 14, 2023Date of Patent: April 23, 2024Assignee: CHAMP VISION DISPLAY INC.Inventors: Chung-Hao Wu, Hsin-Hung Lee, Chin-Ku Liu, Chun-Chien Liao, Wei-Jhe Chien
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Publication number: 20240128353Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11958996Abstract: A protection tape includes a base film, an antistatic layer and an adhesive layer. The antistatic layer is located on the base film. The surface impedance of the antistatic layer is less than 1E+9?, and the antistatic layer includes a first resin and conductive materials dispersed in the first resin. The conductive materials include at least one of metal ions and carbon. The adhesive layer is located on a corona treated surface of the base film. The protection tape provided by the present disclosure has the advantage of having resistant to corona treatment.Type: GrantFiled: July 14, 2022Date of Patent: April 16, 2024Assignee: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Chun-Che Tsao, Cheng-Hung Chen
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Publication number: 20240112928Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: An-Hsuan Lee, Chen-Hao Wu, Chun-Hung Liao, Huang-Lin Chao
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Publication number: 20240021535Abstract: A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source/drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source/drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source/drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features.Type: ApplicationFiled: July 13, 2022Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lin-Yu Huang, Chun-Hung Liao
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Publication number: 20230395504Abstract: Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu Pei Chen, Chia-Hao Chang, Shin-Yi Yang, Chia-Hung Chu, Po-Chin Chang, Shuen-Shin Liang, Chun-Hung Liao, Yuting Cheng, Hung-Yi Huang, Harry Chien, Pinyen Lin, Sung-Li Wang
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Publication number: 20230356356Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hung Liao, Chen-Hao Wu, An-Hsuan Lee, Huang-Lin Chao
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Publication number: 20230347471Abstract: A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: An-Hsuan Lee, Ming-Shiuan She, Chen-Hao Wu, Chun-Hung Liao, Shen-Nan Lee, Teng-Chun Tsai
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Publication number: 20230343638Abstract: A semiconductor device structure includes a gate structure formed over a substrate. The semiconductor device structure also includes a source/drain structure formed beside the gate structure. The semiconductor device structure further includes a contact structure formed over the source/drain structure. The semiconductor device structure also includes a first cap layer formed over the contact structure. The semiconductor device structure further includes a dielectric structure extending from a top surface of the first cap layer into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.Type: ApplicationFiled: July 5, 2023Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung LIAO, Lin-Yu HUANG, Chia-Hao CHANG, Huang-Lin CHAO
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Publication number: 20230298949Abstract: In-situ defect count detection in post chemical mechanical polishing (post-CMP) is provided. Post-CMP is performed, in-situ and according to a recipe, on a surface of a semiconductor wafer within a post-CMP chamber. A light signal is scanned over a target area of the surface of the semiconductor wafer and a reflected light signal reflected from the target area is detected. A defect count of defects present in the target area is determined based on the reflected light signal reflected from the target area.Type: ApplicationFiled: March 16, 2022Publication date: September 21, 2023Inventors: Chun-Hung LIAO, Jeng-Chi LIN, Chi-Jen LIU, Liang-Guang CHEN, Huang-Lin CHAO
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Publication number: 20230290641Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Inventors: CHUN-HUNG LIAO, CHUNG-WEI HSU, TSUNG-LING TSAI, CHEN-HAO WU, AN-HSUAN LEE, SHEN-NAN LEE, TENG-CHUN TSAI, HUANG-LIN CHAO
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Patent number: 11752592Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.Type: GrantFiled: July 16, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hung Liao, Chen-Hao Wu, An-Hsuan Lee, Huang-Lin Chao
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Patent number: 11756825Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.Type: GrantFiled: November 20, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shen-Nan Lee, Teng-Chun Tsai, Chen-Hao Wu, Chu-An Lee, Chun-Hung Liao, Tsung-Ling Tsai
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Patent number: 11735470Abstract: A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a source/drain structure formed beside the gate structure. The structure also includes a contact structure formed over the source/drain structure. The structure also includes a dielectric structure extending into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.Type: GrantFiled: November 13, 2020Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hung Liao, Lin-Yu Huang, Chia-Hao Chang, Huang-Lin Chao
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Patent number: 11719232Abstract: A driving system for driving piezoelectric pump includes one or more mechanical devices and a driving circuit system electrically connected to the at least one mechanical device. The driving circuit system includes a pump-driving unit, a linear voltage-stabilizing unit, a microcontroller unit, a current-sensing unit, and a connection unit. The microcontroller unit generates a first signal, a second signal, and a third signal, and the pump-driving unit receives these signals to drive the mechanical device. The current-sensing unit receives a fourth signal transmitted by the pump-driving unit to obtain an actuation current value of the mechanical device. The linear voltage-stabilizing unit, the current-sensing unit, and the microcontroller unit are coupled to each other through a fifth signal and a sixth signal. The connection unit and the microcontroller unit are coupled to each other through a reset signal, a seventh signal, and an eighth signal provided by the microcontroller unit.Type: GrantFiled: April 20, 2021Date of Patent: August 8, 2023Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Shih-Chang Chen, Che-Wei Huang, Chun-Hung Liao, Wei-Chuan Liao, Chi-Feng Huang, Yung-Lung Han, Tsung-I Lin, Chin-Wen Hsieh