Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer.

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract: A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer.

Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.

Abstract: A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element.

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract: A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure.

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

Abstract: A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency.

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.