Patents by Inventor Chun Wang
Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984465Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a boundary deep trench isolation (BDTI) structure disposed at boundary regions of a pixel region surrounding a photodiode. The BDTI structure has a ring shape from a top view and two columns surrounding the photodiode with the first depth from a cross-sectional view. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel region overlying the photodiode, the MDTI structure extending from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure has three columns with the second depth between the two columns of the BDTI structure from the cross-sectional view. The MDTI structure is a continuous integral unit having a ring shape.Type: GrantFiled: August 9, 2022Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Chuang Wu, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Yen-Ting Chiang, Chun-Yuan Chen, Shen-Hui Hong
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Publication number: 20240154520Abstract: A power factor correction (PFC) converter comprises an inductor, a main switch, a voltage divider, a diode, and a controller. The main switch controls the inductor performing magnetization and demagnetization, wherein a voltage difference between two ends of the main switch is a switch voltage. The voltage divider divides the switch voltage and generates a division voltage. The controller performs the following operations periodically in general mode: turning on the main switch; turning off the main switch after the main switch is turned on for a period of time; obtaining the switch voltage according to the division voltage, and determining the period of time for which the main switch is turned on next time according to the switch voltage and a predetermined output voltage of the PFC converter; and obtaining an output voltage according to the switch voltage during a period of time after the main switch is turned off.Type: ApplicationFiled: March 30, 2023Publication date: May 9, 2024Applicant: Diodes IncorporatedInventors: Haoming Chen, Yi-Chun Wang, Koyen Lee, Feng-Jung Huang
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Publication number: 20240153949Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
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Publication number: 20240153942Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Lun CHIEN, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
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Publication number: 20240148661Abstract: A heat and acid resistant probiotics microsphere having a size from 20 to 250 ?m that can readily be incorporated into food or beverages that subsequently undergo thermal treatment. The synbiotic core includes a seed layer formed from at least one polysaccharide. A probiotic microorganism is coated on the seed layer. An acid-resistant shell layer is positioned over the synbiotic core, the acid-resistant shell layer comprising one or more pH-responsive polymers. A heat-resistant bilayer shell is positioned over the acid-resistant shell layer, the heat-resistant bilayer shell including an inner shell layer and an outer shell layer, wherein the inner shell layer includes a heat-resistant liposome layer and the outer layer includes a heat-resistant disaccharide or polysaccharide.Type: ApplicationFiled: November 1, 2023Publication date: May 9, 2024Inventors: Joo Ann EWE, Chun Hay KO, Tsz Wai NG, Ka Man TSE, Mu WANG
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Publication number: 20240150652Abstract: The disclosure relates to a quantum dot structure. The quantum dot structure includes a quantum dot and a cloud-like shell covering a portion of the quantum dot and having an irregular outer surface. The quantum dot includes: a core; a first shell discontinuously around a core surface of the core; and a second shell between the core and the first shell and encapsulating the core surface of the core, wherein the second shell has an irregular outer surface.Type: ApplicationFiled: October 31, 2023Publication date: May 9, 2024Inventors: Pei Cong YAN, Chia-Chun HSIEH, Huei Ping WANG, Hung-Chun TONG, Yu-Chun LEE
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Patent number: 11978372Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for synchronized dual eye variable refresh rate update for a VR display. A display processor obtains an indication of a synchronous flush or an asynchronous flush with respect to a first DPU and/or a second DPU. The display processor determines whether a first flush operation and/or a second flush operation is available at a time instance, where the first flush operation and the second flush operation are associated with the first DPU and/or the second DPU. The display processor performs, based on a VSync instance, the first flush operation and/or the second flush operation based on whether the first flush operation and/or the second flush operation are available at the time instance and based on the indication of the synchronous flush or the asynchronous flush.Type: GrantFiled: May 16, 2023Date of Patent: May 7, 2024Assignee: QUALCOMM IncorporatedInventors: Sreekanth Modaikkal, Kumar Saurabh, Kalyan Thota, Vishnuvardhan Prodduturi, Chun Wang
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Publication number: 20240145691Abstract: The present invention is related to a novel positive electrode active material for lithium-ion battery. The positive electrode active material is expressed by the following formula: Li1.2NixMn0.8-x-yZnyO2, wherein x and y satisfy 0<x?0.8 and 0<y?0.1. In addition, the present invention provides a method of manufacturing the positive electrode active material. The present invention further provides a lithium-ion battery which uses said positive electrode active material.Type: ApplicationFiled: March 14, 2023Publication date: May 2, 2024Inventors: CHUAN-PU LIU, YIN-WEI CHENG, SHIH-AN WANG, BO-LIANG PENG, CHUN-HUNG CHEN, JUN-HAN HUANG, YI-CHANG LI
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Publication number: 20240145908Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and an antenna structure is stacked on the carrier structure via conductors, where at least one through hole is formed on and penetrating through the antenna structure, and an insulating support body is formed between the carrier structure and the antenna structure, so that the insulating support body is correspondingly formed at the through hole and/or an edge of the antenna structure, and the through hole is free from being filled up by the insulating support body, such that the through hole has an air medium. The design of the through hole allows the characteristic of the dielectric constant of air being 1 to be utilized so as to reduce the signal loss and the signal offset, thereby facilitating the signal transmission of the antenna body.Type: ApplicationFiled: December 27, 2022Publication date: May 2, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yi-Chun LAI, Hsuan-Jen WANG, Rung-Jeng LIN
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Publication number: 20240145554Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20240142794Abstract: A stereo projection screen including a scattering screen having a scattering structure layer, a phase retardation layer disposed between the scattering structure layer and the polarized projector, and a metal reflection layer covering at least a part of the scattering structure layer is provided. The scattering structure layer and the phase retardation layer are arranged in a first display area and a second display area of the stereo projection screen. The metal reflection layer is arranged in at least one of the first display area and the second display area. A first image light beam having a first polarization state has a second polarization state after being transmitted to the first display area and leaving the stereo projection screen. A second image light beam having the first polarization state still has the first polarization state after being transmitted to the second display area and leaving the stereo projection screen.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Applicant: Coretronic CorporationInventors: Chung-Yang Fang, Wen-Chun Wang, Bo-Han Cheng
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Publication number: 20240145461Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.Type: ApplicationFiled: October 4, 2023Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Ker-Yih Kao, Tong-Jung Wang, Wen-Chieh Lin, Ming-Chun Tseng, Yi-Hung Lin
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Publication number: 20240145498Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.Type: ApplicationFiled: January 4, 2023Publication date: May 2, 2024Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240144568Abstract: Apparatuses, systems, and techniques are presented to generate digital content. In at least one embodiment, one or more neural networks are used to generate video information based at least in part upon voice information and a combination of image features and facial landmarks corresponding to one or more images of a person.Type: ApplicationFiled: September 6, 2022Publication date: May 2, 2024Inventors: Siddharth Gururani, Arun Mallya, Ting-Chun Wang, Jose Rafael Valle da Costa, Ming-Yu Liu
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Patent number: 11974367Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.Type: GrantFiled: October 4, 2022Date of Patent: April 30, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
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Patent number: 11971796Abstract: An approach is provided in which the approach builds a combination model that includes a normal status model and an abnormal status model. The normal status model is built from a set of time-sequenced normal status records and the abnormal status model is built from a set of time-sequenced abnormal status records. The approach computes a set of time-sequenced coefficient combination values of the normal status model and the abnormal status model based on applying a set of fitting coefficient characteristics to the normal status model and the abnormal status model. The approach performs goal seek analysis on a system using the combination model and the set of time-sequenced coefficient combination values.Type: GrantFiled: May 18, 2021Date of Patent: April 30, 2024Assignee: International Business Machines CorporationInventors: Xiao Ming Ma, Si Er Han, Lei Gao, A Peng Zhang, Chun Lei Xu, Rui Wang, Jing James Xu
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Patent number: 11974371Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.Type: GrantFiled: July 29, 2021Date of Patent: April 30, 2024Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Yu-Hsiang Wang, Che-Wei Yeh, Keko-Chun Liang, Yong-Ren Fang, Yi-Chuan Liu
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Patent number: 11974228Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.Type: GrantFiled: June 10, 2021Date of Patent: April 30, 2024Assignee: MediaTek Singapore Pte. Ltd.Inventors: Kai Ying Lu, Hung-Tao Hsieh, Yen-Shuo Lu, Chao-Chun Wang, James Chih-Shi Yee, Yongho Seok
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Patent number: 11973163Abstract: A light emitting device includes an epitaxial structure and first and second electrodes on a side of the epitaxial structure. The epitaxial structure includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode is disposed on the epitaxial structure to be electrically connected with the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure to be electrically connected with the second-type semiconductor layer. The second electrode is in ohmic contact with a second-type window sublayer of the second-type semiconductor layer.Type: GrantFiled: January 20, 2023Date of Patent: April 30, 2024Assignee: Tianjin Sanan Optoelectronics Co., Ltd.Inventors: ChingYuan Tsai, Chun-Yi Wu, Fulong Li, Duxiang Wang, Chaoyu Wu, Wenhao Gao, Xiaofeng Liu, Weihuan Li, Liming Shu, Chao Liu
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Publication number: 20240134287Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU