Patents by Inventor Chun Wang
Chun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11962949Abstract: A method of performing air pollution estimation is provided. The method is to be implemented using a processor of a computer device and includes: generating a spectral image based on an original color image of an environment under test using a spectral transformation matrix; supplying the spectral image as an input into an estimating model for air pollution estimation; and obtaining an estimation result from the estimating model indicating a degree of air pollution of the environment under test.Type: GrantFiled: July 22, 2021Date of Patent: April 16, 2024Assignee: National Chung Cheng UniversityInventors: Hsiang-Chen Wang, Chia-Cheng Huang, Ting-Chun Men
-
Patent number: 11960191Abstract: A conductive structure is applied to an e-paper device, which includes a driving substrate and an e-paper film. The e-paper film is disposed on the driving substrate, and includes a transparent substrate, a common electrode layer, and a display medium layer disposed between the common electrode layer and the driving substrate. The common electrode layer is disposed on one side of the transparent substrate facing the driving substrate. The display medium layer includes a through hole. The conductive structure is disposed in the through hole and includes a conductive member and at least one spacer. The conductive member is electrically connected to the driving substrate and the common electrode layer. The spacer is disposed in/on the conductive member, and contacts with the driving substrate and the common electrode layer. An e-paper device with the conductive structure is also disclosed.Type: GrantFiled: July 9, 2021Date of Patent: April 16, 2024Assignee: SES-IMAGOTAG SAInventors: Chin-An Yang, Yew-Chun Wang
-
Publication number: 20240120444Abstract: A light-emitting device includes a substrate, a semiconductor epitaxial structure, and an etch stop layer. The substrate has a first surface and a second surface opposite to the first surface. The semiconductor epitaxial structure has a side surface that has a roughened structure formed with protrusions, and includes a first type semiconductor layer, an active layer, and a second type semiconductor layer disposed on the first surface of the substrate in such order. The etch stop layer is disposed on a surface of the semiconductor epitaxial structure away from the substrate for preventing an etching solution from etching the semiconductor epitaxial structure. A light-emitting package and a light-emitting apparatus are also provided. A method for manufacturing a light-emitting device is also provided.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: Wuqi SHEN, Die HU, Shaohua WU, Lingfei WANG, Zhendong NING, Chen Kang HSIEH, Chun-I CHANG, Duxiang WANG
-
Publication number: 20240119603Abstract: The present disclosure provides a ball tracking system and method. The ball tracking system includes camera device and processing device. The camera device is configured to generate a plurality of video frame data, wherein the video frame data includes image of ball. The processing device is electrically coupled to the camera device and is configured to: recognize the image of the ball from the plurality of video frame data to obtain 2D estimation coordinate of the ball at first frame time and utilize 2D to 3D matrix to convert the 2D estimation coordinate into first 3D estimation coordinate; utilize model to calculate second 3D estimation coordinate of the ball at the first frame time; and calibrate according to the first 3D estimation coordinate and the second 3D estimation coordinate to generate 3D calibration coordinate of the ball at the first frame time.Type: ApplicationFiled: November 17, 2022Publication date: April 11, 2024Inventors: Rong-Sheng WANG, Shih-Chun CHOU, Hsiao-Chen CHANG
-
Publication number: 20240120294Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.Type: ApplicationFiled: December 21, 2023Publication date: April 11, 2024Inventors: Shu-Shen YEH, Chin-Hua WANG, Kuang-Chun LEE, Po-Yao LIN, Shyue-Ter LEU, Shin-Puu JENG
-
Publication number: 20240120241Abstract: The present invention provides an electrostatic charge detecting packaging device comprising a carrier, multiple dies, and multiple electrostatic-charge-sensitive components; the carrier has a surface; the dies are mounted on the surface of the carrier; and the electrostatic-charge-sensitive components are mounted on the surface of the carrier; since an electrostatic voltage tolerance of each of the electrostatic-charge-sensitive components is lower than an electrostatic voltage tolerance of each of the dies, accumulated electrostatic charges are more likely to discharge towards the electrostatic-charge-sensitive components than towards the dies, and as such, by electrically testing whether the electrostatic-charge-sensitive components are functioning normally when packaging the dies, the present invention allows personnel to debug for knowing which packaging steps exactly cause more serious problems that lead to damaging electrostatic discharges in the dies.Type: ApplicationFiled: November 30, 2022Publication date: April 11, 2024Inventors: Chung-Hsiung HO, Chien-Chun Wang, Li-Qiang Ye, Chi-Hsueh Li
-
Publication number: 20240116853Abstract: 2-hydroxy-5-[2-(4-(trifluoromethylphenyl)ethylamino)]benzoic acid crystal forms and a preparation method therefor are proposed. Crystal form I is a monoclinic crystal system, which has a Pc space group and can be obtained by slow cooling, evaporating the solvent at a constant temperature, evaporating the solvent at an increased temperature, or adding an anti-solvent. Crystal form II is a triclinic crystal system, which has a P1 space group and can be obtained by rapid cooling or freeze-drying. According to the method, the process is simple, costs are low, and the yield exceeds 90%; and the crystal forms of the crystal forms I and II have high purity, the crystal shapes thereof are intact, and have excellent fluidity, facilitating preparation, particularly the preparation of a pharmaceutical preparation for preventing and/or treating degenerative diseases of the central nervous system. Furthermore, the two crystal forms have a better apparent solubility than that of raw materials.Type: ApplicationFiled: December 6, 2021Publication date: April 11, 2024Inventors: Xinliang XU, Guoqing ZHANG, Chenghan ZHUANG, Lei WANG, Byoung Joo GWAG, Chun San AHN, Jing Yu JIN
-
Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
-
Patent number: 11955441Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.Type: GrantFiled: March 28, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
-
Patent number: 11955191Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.Type: GrantFiled: June 2, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
-
Patent number: 11955335Abstract: In a method of coating a photo resist over a wafer, dispensing the photo resist from a nozzle over the wafer is started while rotating the wafer, and dispensing the photo resist is stopped while rotating the wafer. After starting and before stopping the dispensing the photo resist, a wafer rotation speed is changed at least 4 times. During dispensing, an arm holding the nozzle may move horizontally. A tip end of the nozzle may be located at a height of 2.5 mm to 3.5 mm from the wafer.Type: GrantFiled: August 8, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung-Hung Feng, Hui-Chun Lee, Sheng-Wen Jiang, Shih-Che Wang
-
Patent number: 11957061Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
-
Patent number: 11953078Abstract: A gear module includes a rotating cylinder, a first planetary gear set, a second planetary gear set, a concave-convex structure, and a limit bearing set. The first planetary gear set is accommodated in the rotating cylinder and includes a driven gear; the second planetary gear set includes a positioning frame, second planetary gears pivoted to a positioning frame, a driven gear engaged with the second planetary gears, and the positioning frame has a through hole; the concave-convex structure includes a convex column extended from the rotating cylinder and a concave hole formed on the positioning frame, the convex column is plugged into the concave hole; the limit bearing set includes a first ball bearing sheathing the driven gear and mounted between the driven gear and the through hole, and a second ball bearing sheathing the convex column and mounted between the convex column and the concave hole.Type: GrantFiled: August 16, 2023Date of Patent: April 9, 2024Assignee: SHA YANG YE INDUSTRIAL CO., LTD.Inventors: Feng-Chun Tsai, Ming-Han Tsai, Chin-Fa Lu, Kai-Hsien Wang
-
Publication number: 20240112957Abstract: A fabrication method is disclosed that includes: forming a first metal layer over first and second semiconductor structures; forming a first patterned photolithographic layer with an opening that exposes a portion of the first metal layer over the first semiconductor structure but not to a boundary between semiconductor structures; removing the exposed portion of the first metal layer; forming a second metal layer over the first and second semiconductor structures; forming a second patterned photolithographic layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not to the boundary; removing the exposed portion of the first and second metal layers; wherein a barrier structure is generated between the first and second semiconductor structures that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer.Type: ApplicationFiled: January 12, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Xuan Wang, Cheng-Chun Tseng, Yi-Chun Chen, Yu-Hsien Lin, Ryan Chia-Jen Chen
-
Publication number: 20240113262Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the platType: ApplicationFiled: September 1, 2023Publication date: April 4, 2024Inventors: Hsin-Ying WANG, Hui-Chun YEH, Jhih-Yong YANG, Chen OU, Cheng-Lin LU
-
Publication number: 20240113043Abstract: A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.Type: ApplicationFiled: April 20, 2023Publication date: April 4, 2024Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Wen-Chun You
-
Patent number: 11944970Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.Type: GrantFiled: June 10, 2019Date of Patent: April 2, 2024Assignees: INSTANT NANOBIOSENSORS, INC., INSTANT NANOBIOSENSORS CO., LTD.Inventors: Yu-Chung Huang, Yi-Li Sun, Ting-Chou Chang, Jhy-Wen Wu, Nan-Kuang Yao, Lai-Kwan Chau, Shau-Chun Wang, Ying Ting Chen
-
Patent number: 11948805Abstract: An etching method for selectively etching a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate.Type: GrantFiled: October 26, 2020Date of Patent: April 2, 2024Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.Inventors: Xin Wu, Chun Wang, Bo Zheng, Zhenguo Ma
-
Publication number: 20240101768Abstract: Disclosed are a vibrating diaphragm of a sound-producing apparatus and the sound-producing apparatus. The vibrating diaphragm includes a polyurethane rubber film layer and the polyurethane rubber film layer includes a block polymer formed by soft segment portions and hard segment portions that are arranged alternately, wherein each of the soft segment portions includes polyhydric alcohol and each of the hard segment portions includes isocyanate and a chain extender, and the polyurethane rubber is represented by a structural formula as follows: wherein R is the chain extender, R1 is polyhydric alcohol and n is a natural number. (FIG.Type: ApplicationFiled: December 25, 2019Publication date: March 28, 2024Applicant: Goertek Inc.Inventors: Shuqiang Wang, Fengguang Ling, Chun Li, Chunfa Liu
-
Publication number: 20240107414Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN