Patents by Inventor Chun-Wei Chang

Chun-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096701
    Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
    Type: Application
    Filed: May 17, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Publication number: 20240087951
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11926266
    Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: March 12, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Shih-Wei Yeh, Chien-Chih Lin, Yi-Ming Chou, Chun-Chieh Chang
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11924965
    Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Jian-Hong Lin, Shu-Yuan Ku, Wei-Cheng Liu, Yinlung Lu, Jun He
  • Publication number: 20240071981
    Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Publication number: 20240047345
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
  • Publication number: 20230402315
    Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Wei-Chao CHIU, Yu-Wen CHEN, Yong-Jin LIOU, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20230402385
    Abstract: A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong LIN, Yinlung LU, Jun HE, An Shun TENG, Chun-Wei CHANG
  • Patent number: 11835725
    Abstract: A head-mounted display device assembly and an external adjustment module are provided. The head-mounted display device assembly includes a head-mounted display device and the external adjustment module. The head-mounted display device has a first lens and a second lens corresponding to both eyes, and also has a driven mechanism. The first lens and the second lens are respectively coupled to the driven mechanism. The external adjustment module is used for assembling and electrically connecting to the head-mounted display device, and includes a driving element and a transmission element. In a coupling state, the transmission element is coupled to the driving element and the driven mechanism, and the driving element drives the driven mechanism via the transmission element to adjust a distance between the first lens and the second lens. In a separation state, at least one of the driving element and the driven mechanism is separated from the transmission element.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: December 5, 2023
    Assignee: HTC Corporation
    Inventors: Chun-Wei Chang, Ying-Chieh Huang, Pei-Yu Su, Yen-Te Chiang, Chun-Kai Yang, Wei-Ting Hsiao, Yien-Chun Kuo
  • Patent number: 11830806
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Hsuan-Ming Huang, Jian-Hong Lin, Ming-Hong Hsieh, Mingni Chang, Ming-Yih Wang
  • Publication number: 20230345622
    Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: CHUN-WEI CHANG, JIAN-HONG LIN, SHU-YUAN KU, WEI-CHENG LIU, YINLUNG LU, JUN HE
  • Publication number: 20230334220
    Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Hsien Yu TSENG, Amit KUNDU, Chun-Wei CHANG, Szu-Lin LIU, Sheng-Feng LIU
  • Patent number: 11791729
    Abstract: The technology described herein is directed to a DC input power supply unit with an auxiliary boost control circuit (or controller) that facilitates continuous supply of power to a standby output load of the power supply unit in a bootloader mode. More specifically, the auxiliary boost circuit (or controller) is configured to assume control of a primary power boost stage from a primary controller in a bootloader mode so that the power supply unit can continue to supply power to the standby output with a protection function regardless of the state of the power supply unit or primary controller.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: October 17, 2023
    Assignee: Astec International Limited
    Inventors: Chih-hao Hsu, Chang-Chieh Yu, Carl Walker, Chun-Wei Chang, Po-Tso Chen
  • Patent number: 11787014
    Abstract: A vice jaw deflecting structure, comprising a vice main body, a lead screw positioning seat, a lead screw, a first flexible jaw set and a second flexible jaw set; the guide slot of the vice main body has a bottom surface, a first side wall surface, and a second side wall surface; the first flexible jaw set and the second flexible jaw set have a slide, a jaw and a limiting component; the slide is configured with a limiting block protruding toward the jaw, the limiting block protrudes toward the lead screw positioning seat and is formed with a -shaped stop block having a curved top view; the jaw bottom surface has a first convex wall surface and a second convex wall surface matching and contacting the first side wall surface and the second side wall surface.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 17, 2023
    Inventor: Chun-Wei Chang
  • Publication number: 20230324699
    Abstract: A head-mounted display device assembly and an external adjustment module are provided. The head-mounted display device assembly includes a head-mounted display device and the external adjustment module. The head-mounted display device has a first lens and a second lens corresponding to both eyes, and also has a driven mechanism. The first lens and the second lens are respectively coupled to the driven mechanism. The external adjustment module is used for assembling and electrically connecting to the head-mounted display device, and includes a driving element and a transmission element. In a coupling state, the transmission element is coupled to the driving element and the driven mechanism, and the driving element drives the driven mechanism via the transmission element to adjust a distance between the first lens and the second lens. In a separation state, at least one of the driving element and the driven mechanism is separated from the transmission element.
    Type: Application
    Filed: October 11, 2022
    Publication date: October 12, 2023
    Applicant: HTC Corporation
    Inventors: Chun-Wei Chang, Ying-Chieh Huang, Pei-Yu Su, Yen-Te Chiang, Chun-Kai Yang, Wei-Ting Hsiao, Yien-Chun Kuo
  • Publication number: 20230290637
    Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 14, 2023
    Inventors: Wei-Chao CHIU, Yong-Jin LIOU, Yu-Wen CHEN, Chun-Wei CHANG, Ching-Sen KUO, Feng-Jia SHIU
  • Patent number: 11757684
    Abstract: A retiming circuit module, a signal transmission system, and a signal transmission method are provided. The retiming circuit module includes a path control circuit and a multipath signal transmission circuit. The multipath signal transmission circuit includes built-in first signal transmission path and second signal transmission path. The multipath signal transmission circuit may perform first signal transmission between an upstream device and a downstream device based on a first signal transmission frequency and the second signal transmission path. During a period of performing the first signal transmission, the path control circuit may detect a first data sequence transmitted between the upstream device and the downstream device.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: September 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chun-Wei Chang, Ching-Jui Hsiao, Jen-Chu Wu, Yuwei Kuo
  • Patent number: 11742604
    Abstract: An easy-lock connector with unlock structure includes a rubber core, a housing and plural terminals. The rubber core includes a first body, acting parts and terminal grooves in which the terminals are arranged. Each of the action parts includes a first stop body and a third stop body. An opening is formed between the first stop body and the third stop body. The housing includes a second body and pressing parts. When the action parts are pressed by an external force, the action parts will be deformed. Then, a flexible printed circuit board will be unlocked on the first body, and the action parts are stopped by the first stop body and the third stop body to stop continuing to deform. When the action parts are not pressed by the external force, the circuit board is locked on the first body.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: August 29, 2023
    Assignee: P-TWO INDUSTRIES INC.
    Inventors: Chun-Wei Chang, Yu-Yi Lin
  • Publication number: 20230246376
    Abstract: A module connector comprising a first connecting component and a second connecting component. The first connecting component includes a first base, a plurality of first conductors and a plurality of first clamping parts. The first base includes a first body, a plurality of first cable grooves, a plurality of first through holes and a plurality of third cable grooves. The first body forms the first cable grooves and the third cable grooves to be able to accommodate the cables. The central axes of the first through holes are at a first angle with the first cable grooves and pass through the first body, and one ends of the first through holes communicate with the first cable grooves. The first conductors are disposed in the first cable grooves. The second connecting component can connect with the first connecting component through the cables, so that at least one of signals and power can be transmitted between the second connecting component and the circuit board.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 3, 2023
    Inventors: HSIEN-CHANG LIN, CHUN-WEI CHANG, CHIA-CHEN WEI