Patents by Inventor Chun-Wei Chang

Chun-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220286052
    Abstract: The technology described herein is directed to a DC input power supply unit with an auxiliary boost control circuit (or controller) that facilitates continuous supply of power to a standby output load of the power supply unit in a bootloader mode. More specifically, the auxiliary boost circuit (or controller) is configured to assume control of a primary power boost stage from a primary controller in a bootloader mode so that the power supply unit can continue to supply power to the standby output with a protection function regardless of the state of the power supply unit or primary controller.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 8, 2022
    Inventors: Chih-hao HSU, Chang-Chieh YU, Carl Walker, Chun-Wei Chang, Po-Tso Chen
  • Patent number: 11411033
    Abstract: A method includes forming a first photoresist layer on a front side of a device substrate and having first trenches spaced apart from each other. A first implantation process is performed using the first photoresist layer as a mask to form first isolation regions in the device substrate. A second photoresist layer is formed on the front side and has second trenches. A second implantation process is performed using the second photoresist layer as a mask to form second isolation regions in the device substrate and crossing over the first isolation regions. A third photoresist layer is formed on the front side and has third trenches spaced apart from each other. A third implantation process is performed using the third photoresist layer as a mask to form third isolation regions in the device substrate and crossing over the first isolation regions but spaced apart from the second isolation regions.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chun-Wei Chang, Ching-Sen Kuo, Feng-Jia Shiu
  • Publication number: 20220215151
    Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Inventors: Hsien Yu TSENG, Amit KUNDU, Chun-Wei CHANG, Szu-Lin LIU, Sheng-Feng LIU
  • Patent number: 11381169
    Abstract: The technology described herein is directed to a DC input power supply unit with an auxiliary boost control circuit (or controller) that facilitates continuous supply of power to a standby output load of the power supply unit in a bootloader mode. More specifically, the auxiliary boost circuit (or controller) is configured to assume control of a primary power boost stage from a primary controller in a bootloader mode so that the power supply unit can continue to supply power to the standby output with a protection function regardless of the state of the power supply unit or primary controller.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 5, 2022
    Assignee: Astec International Limited
    Inventors: Chih-hao Hsu, Chang-Chieh Yu, Carl Walker, Chun-Wei Chang, Po-Tso Chen
  • Patent number: 11340641
    Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 24, 2022
    Assignee: MediaTek Inc.
    Inventors: Chun-Wei Chang, Song-Yu Yang, Ang-Sheng Lin
  • Publication number: 20220149565
    Abstract: The invention provides an easy lock connector with unlock structure applied to a flat wire and a circuit board. The flat wire has a notch and a ground wire on the two sides of a head end respectively. The easy-lock connector includes an upper housing, a lower housing, a rubber core and a terminal. After the notch of the flat wire is buckled by a stopper of the lower housing, by pressing a pressing member of the upper housing, the pressing member applies an external force to an elastic member of the lower housing to deform the elastic member. An extension arm of the lower housing is linked by the elastic member to cause the stopper to act in one direction so as to release the state of the stopper from locking the gap. In another embodiment, the easy-lock connector can also achieve an electromagnetic shielding effect by adding a shielding iron shell.
    Type: Application
    Filed: September 8, 2021
    Publication date: May 12, 2022
    Inventors: HSIEN CHANG LIN, CHUN WEI CHANG
  • Publication number: 20220149849
    Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
    Type: Application
    Filed: September 29, 2021
    Publication date: May 12, 2022
    Applicant: MEDIATEK INC.
    Inventors: Ang-Sheng Lin, Chun-Wei Chang, Tzu-Chan Chueh
  • Patent number: 11327322
    Abstract: A head mounted display device, including a main body, a headband component, two earphone components, and two driving modules, is provided. The headband component includes two opposite headband connectors. The two headband connectors are respectively rotatably arranged on two opposite sides of the main body along a first axis. The two earphone components respectively include two earphone connectors. The two earphone connectors are respectively rotatably arranged on the two sides of the main body along two parallel second axes, and the two earphone connectors are located beside the two headband connectors of the headband component. The two driving modules are respectively arranged between the two headband connectors and the two earphone connectors, and the two earphone connectors are linked to the two headband connectors.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 10, 2022
    Assignee: HTC Corporation
    Inventors: Chou-Wei Wu, Ying-Chieh Huang, Yen-Cheng Lin, Tung-Ting Cheng, Chun-Wei Chang
  • Publication number: 20220107794
    Abstract: A program compilation system for stackable visualization control is provided for generating a driver program to execute a linking control of automated devices of different functions. The system includes a block module, a card module and a compilation module. The block module has conditional blocks, each being an operation instruction for modularizing each of the automated devices and setting a parameter. The card module has card options corresponding to the automated devices and collected and combined with the respective conditional blocks. When a user selects the card options, the compilation module loads the corresponding conditional blocks for the user to select the required conditional blocks and sets the parameters before forming a program module according to movements and stacking of visualization to compile and generate the driver program. Therefore, end users can improve the freedom and compatibility of a linked operation between the automated devices for customization.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Inventors: CHIEH-YUAN CHENG, CHUN-WEI CHANG, PANG-YEN YOU
  • Publication number: 20220103071
    Abstract: The technology described herein is directed to a DC input power supply unit with an auxiliary boost control circuit (or controller) that facilitates continuous supply of power to a standby output load of the power supply unit in a bootloader mode. More specifically, the auxiliary boost circuit (or controller) is configured to assume control of a primary power boost stage from a primary controller in a bootloader mode so that the power supply unit can continue to supply power to the standby output with a protection function regardless of the state of the power supply unit or primary controller.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: Astec International Limited
    Inventors: Chih-hao HSU, Chang-Chieh YU, Carl Walker, Chun-Wei Chang, Po-Tso Chen
  • Patent number: 11288437
    Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien Yu Tseng, Chun-Wei Chang, Szu-Lin Liu, Amit Kundu, Sheng-Feng Liu
  • Patent number: 11277119
    Abstract: Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: March 15, 2022
    Assignee: NXP USA, Inc.
    Inventors: Namsik Ryu, Margaret A Szymanowski, Chun-Wei Chang
  • Patent number: 11251555
    Abstract: A floating connector includes a shell, a plurality of electrodes, two buckle members and a floating member. The shell has an accommodating space and a plurality of openings. The electrodes are disposed in the accommodating space and penetrate the openings to protrude from the openings. The buckle members are respectively disposed on two sides of the accommodating space. Each of the buckle members includes a fixed part, a contacting part, and an elastic part. The floating member includes a body, a plurality of electrode notches, and a bump. The electrode notches are formed on one side of the body that near the electrodes for receiving the electrodes protruding from the openings. The bump is disposed on the body and correspondingly to the notch, and the width of the bump is not greater than that of the notch, so that the bump is restricted in the notches by the guiding structure.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 15, 2022
    Assignee: P-TWO INDUSTRIES INC.
    Inventors: Hsien-Chang Lin, Chun-Wei Chang
  • Publication number: 20210376085
    Abstract: A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height.
    Type: Application
    Filed: August 5, 2021
    Publication date: December 2, 2021
    Inventors: Jhong-Sheng WANG, Jiaw-Ren SHIH, Chun-Wei CHANG, Sheng-Feng LIU
  • Publication number: 20210320646
    Abstract: Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Inventors: Namsik RYU, Margaret A SZYMANOWSKI, Chun-Wei CHANG
  • Patent number: 11138945
    Abstract: The present disclosure provides a source driver module for driving a display panel. The source drive module includes a source driver circuit, a first conductive wire and a first switch unit. The first conductive wire is electrically connected to the source driver circuit. The first switch unit is connected between the first conductive wire and a first data line of the display panel to conduct current therebetween during a first data outputting period and a second data outputting period, and to interrupt current therebetween during a first switch-off period connecting the first data outputting period and the second data outputting period. The source driver circuit outputs a first voltage signal during the first data outputting period and the first switch-off period; it outputs a second voltage signal during the second data outputting period; and it outputs the first voltage signal during the first switch-off period.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 5, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Jie-Chuan Huang, Chun-Wei Chang, Chia-Ming Wu
  • Publication number: 20210280620
    Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
    Type: Application
    Filed: May 5, 2021
    Publication date: September 9, 2021
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 11114007
    Abstract: A display panel includes multiple data lines, a scan lines, pixel circuit and a driving circuit. The data lines are configured to receive multiple data signals in a display period. There is a buffer period before the display period. The scan line is configured to receive a scan signal during the display period. The pixel circuit is electrically connected to the data lines and the scan line for receiving the data signals and the scan signal. The driving circuit is electrically connected to the data line, and configured to receive multiple charging signals during the buffer period. The charging signals are corresponding to the data lines and gradually increase so that the driving circuit charges the data lines according to the charging signals.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 7, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chun-Wei Chang, Jie-Chuan Huang
  • Patent number: 11107889
    Abstract: A semiconductor device including a substrate having a major surface. The semiconductor device further includes a dielectric material on the major surface of the substrate. The semiconductor device further includes a first plurality of fins extending from the major surface of the substrate, wherein the dielectric material surrounding each fin of the first plurality of fins has a first thickness. The semiconductor device further includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, the dielectric material surround each fin of the second plurality of fins has a second thickness, and the second thickness is different from the first thickness.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhong-Sheng Wang, Jiaw-Ren Shih, Chun-Wei Chang, Sheng-Feng Liu
  • Publication number: 20210265757
    Abstract: A floating connector includes a shell, a plurality of electrodes, two buckle members and a floating member. The shell has an accommodating space and a plurality of openings. The electrodes are disposed in the accommodating space and penetrate the openings to protrude from the openings. The buckle members are respectively disposed on two sides of the accommodating space. Each of the buckle members includes a fixed part, a contacting part, and an elastic part. The floating member includes a body, a plurality of electrode notches, and a bump. The electrode notches are formed on one side of the body that near the electrodes for receiving the electrodes protruding from the openings. The bump is disposed on the body and correspondingly to the notch, and the width of the bump is not greater than that of the notch, so that the bump is restricted in the notches by the guiding structure.
    Type: Application
    Filed: July 9, 2020
    Publication date: August 26, 2021
    Inventors: Hsien-Chang Lin, Chun-Wei Chang